Methods to form metal lines using selective electrochemical deposition

A method of forming a transistor for use in an active matrix liquid crystal display (AMLCD), comprising:

• providing a glass substrate;
• depositing a conductive seed layer on a surface of the glass substrate;
• depositing a resist material on the conductive seed layer;
• patterning the resist layer to expose the conductive seed layer;
• etching exposed portions of the conductive seed layer;
• removing the resist material;
• and
• depositing a metal layer on remaining portions of the conductive seed layer by an electrochemical deposition technique.

A method of forming a transistor for use in an active matrix liquid crystal display (AMLCD), comprising:

• providing a glass substrate;
• forming one or more doped semiconductor layers having source regions and drain regions formed therein;
• forming one or more gate dielectric layers on the one or more doped semiconductor layers;
• forming one or more metal gates on the one or more gate dielectric layers by:
• depositing a conductive seed layer on one or more gate dielectric layers;
• depositing a resist material on the conductive seed layer;
• patterning the resist layer to expose portions of the conductive seed layer;
• depositing a metal layer on the exposed portions of the conductive seed layer by an electrochemical technique;
• and
• removing the resist material;
• depositing an Interlayer dielectric material on the substrate and over the one or more metal gates;
• patterning one or more gate dielectric layers and the interlayer dielectric material to form feature definitions exposing underlying source regions and drain regions;
• and
• depositing a metal layer in the feature definitions to form a contact.

A method of forming a transistor for use in an active matrix liquid crystal display (AMLCD), comprising:

• providing a glass substrate:
• forming one or more doped semiconductor layers having source regions and drain regions formed therein;
• forming one or more gate dielectric layers on the one or more doped semiconductor layers;
• forming one or more metal gates on the one or more gate dielectric layers by:
• depositing a conductive seed layer on the one or more gate dielectric layers;
• depositing a resist material on the conductive seed layer;
• patterning the resist layer to expose the conductive seed layer;
• etching exposed portions of the conductive seed layer;
• removing the resist material;
• and
• depositing a metal layer on remaining portions of the conducive seed layer by an electrochemical technique;
• depositing an interlayer dielectric material on the substrate and over the one or more metal gates;
• patterning one or more gate dielectric layers and the interlayer dielectric material to form feature definitions exposing underlying source regions and drain regions;
• and
• depositing a metal layer in the feature definitions to form a contact.