Methods of incorporating germanium within CMOS process
AssigneeLuxtera, Inc.
InventorsLawrence C. Gunn, III, Giovanni Capellini, Maxime Jean Rattier, Thierry J. Pinguet
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Abstract
Methods for deposition of a Ge layer during a CMOS process on a monolithic device are disclosed. The insertion of the Ge layer enables the conversion of light to electrical signals easily. As a result of this method, standard metals can be attached directly to the Ge in completing an electrical circuit. Vias can also be used to connect to the Ge layer. In a first aspect of the invention, a method comprises the step of incorporating the deposition of Ge at multiple temperatures in a standard CMOS process. In a second aspect of the invention, a method comprises the step of incorporating the deposition of poly-Ge growth in a standard CMOS process.
Claims173
A method for incorporating one or more germanium layers in a standard CMOS flow, comprising:
- providing a silicon-based substrate using a standard CMOS process;
- depositing a first silicon oxynitride (SixOyNz, herein after referred to SON) layer overlying the silicon-based substrate that serves as a mask;
- etching the first SON layer onto the silicon-based substrate to form a trench in the SON, thereby forming a SON patterned substrate as defined by a first region of the SON spaced apart laterally from a second region of the SON and above the silicon-based substrate;
- and
- depositing a first germanium layer into a portion of the trench that is incorporated as part of a CMOS process, the trench being formed by the first region of SON, the silicon-based substrate, and the second region of SON.
Dependencies are inferred from the claim text.