Vertical semiconductor devices

A vertical semiconductor structure, comprising:

• first and second shallow trench isolation regions formed in a substrate comprising a semiconductor material;
• and
• a first vertical transistor formed in the substrate and sandwiched between the first and second shallow trench isolation regions, the first vertical transistor including first and second source/drain regions, a first channel region, a gate region, and a first gate dielectric layer sandwiched between the gate region and the first channel region,
• wherein the first channel region abuts the first and second shallow trench isolation regions via first and second abutting surfaces, respectively, and
• wherein the first and second abutting surfaces are perpendicular to an orientation plane of the semiconductor material of the substrate.

A method for fabricating a vertical semiconductor structure, the method comprising the steps of:

• providing a semiconductor substrate comprising a semiconductor material;
• forming a deep trench in the semiconductor substrate;
• depositing a first gate dielectric layer on a wall of the deep trench;
• filling the deep trench with a filling material and recessing the filling material in the deep trench down to a recess depth;
• removing the first gate dielectric layer on a side wall of the deep trench down to a level lower than the recess depth;
• filing the deep trench with poly silicon and recessing the poly silicon down to a level above the recess depth;
• filling the deep trench with a second dielectric layer and selectively removing the dielectric on a wall of the deep trench so as to form a trench top dielectric layer;
• filling the deep trench with poly silicon;
• forming a first source/drain region and a second source/drain region around and along the depth of the deep trench;
• forming first and second shallow trench isolation regions sandwiching the deep trench in an active region, the first and second shallow trench isolation regions abutting the active region via first and second abutting surfaces, respectively, wherein the first and second abutting surfaces are parallel to each other and are perpendicular to an orientation plane of the semiconductor material of the substrate;
• removing the first gate dielectric layer so as to expose the semiconductor material in the deep trench to the atmosphere;
• chemically etching the exposed semiconductor material in the deep trench;
• depositing a second gate dielectric layer on a side wall of the deep trench;
• and
• forming a gate terminal for the vertical semiconductor structure in the deep trench.