Fabrication process of a trench gate power MOS transistor with scaled channel

A process for forming a trench gate power MOS transistor comprising:

• forming a first epitaxial layer having a first type of conductivity on a semiconductor substrate;
• forming a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second type of conductivity and defining a body region of the transistor;
• forming a gate trench extending into the first and second epitaxial layers;
• countersinking upper portions of the gate trench;
• forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof;
• forming a gate conducting layer on surfaces of the gate dielectric layer for defining a gate electrode, the gate conducting layer having a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein;
• filling the residual cavity of the gate trench with a filler layer;
• removing the gate conducting layer on an upper surface of the second epitaxial layer while using the filler layer as a self-aligned mask;
• oxidizing edge surfaces of the gate conducting layer;
• and
• forming source regions by implanting dopants in the second epitaxial layer body while using the oxidized edge surfaces as a self-aligned mask, and diffusing the implanted dopants in the second epitaxial layer, the body and source regions having an electrical short-circuit therebetween.

A process for forming a trench gate power MOS transistor, the processing comprising:

• forming an epitaxial layer having a first type of conductivity on a semiconductor substrate;
• forming a gate trench in the epitaxial layer;
• countersinking upper portions of the gate trench;
• forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof;
• forming a gate conducting layer on surfaces of the gate dielectric layer for defining a gate electrode, the gate conducting layer having a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein;
• filling the residual cavity of the gate trench with a filler layer;
• removing the gate conducting layer on an upper surface of the epitaxial layer while using the filler layer as a self-aligned mask;
• oxidizing edge surfaces of the gate conducting layer;
• forming a body region in the epitaxial layer by implanting dopants into the epitaxial layer while using the oxidized edge surfaces of the gate conducting layer as a self-aligned mask, and diffusing the implanted dopants in the epitaxial layer;
• and
• forming source regions by implanting dopants in the body region while using the oxidized edge surfaces as a self-aligned mask, and diffusing the implanted dopants in the body region, the body and source regions having an electrical short-circuit therebetween.

A trench gate power MOS transistor comprising:

• a semiconductor substrate;
• an epitaxial layer on said semiconductor substrate and having a first type of conductivity;
• a body region on said epitaxial layer and having a second type of conductivity;
• a gate trench extending into said body region and said epitaxial layer, with upper portions of the gate trench being countersunk;
• a gate dielectric layer on surfaces of the gate trench including the upper portions thereof;
• a gate conducting layer on surfaces of the gate dielectric layer for defining a gate electrode, said gate conducting layer having a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein, with edge surfaces of said gate conducting layer being oxidized;
• and
• a filler layer in the residual cavity of the gate trench;
• source regions in said body region, with said body and source regions having an electrical short-circuit therebetween.