Multiple oxide thicknesses for merged memory and logic applications

A method comprising:

• forming a top device on a top surface of a silicon wafer, wherein the top surface has a (100) crystal plane orientation and the top device includes a top gate separated from the top surface by a top gate oxide;
• and
• forming a trench device on a trench wall of a trench in the silicon wafer, wherein the trench wall has a (110) crystal plane orientation and the trench device includes a trench gate separated from the trench wall by a trench gate oxide, such that a thickness of the top gate oxide is different from a thickness of the trench gate oxide.

A method comprising:

• forming a top layer of SiO2 on a top surface of a silicon wafer, wherein the top surface has a (111) crystal plane orientation, such that the top layer has a top thickness;
• and
• forming a trench layer of SiO2 on a trench wall of the silicon wafer, wherein the trench wall has a (110) crystal plane orientation, such that the trench layer has a trench thickness that is different from the top thickness of the top layer.

A method comprising:

• forming a top layer of SiO2 on a top surface of a silicon wafer, wherein the top surface has a (111) crystalline orientation, such that the top layer has a top thickness;
• and
• forming a trench layer of SiO2 on a trench wall of the silicon wafer, wherein the trench wall has a (110) crystalline orientation, such that the trench layer has a trench thickness that is different from the top thickness of the top layer, wherein forming the top layer of SiO2 and forming the trench layer of SiO2 includes forming the top layer of SiO2 and forming the trench layer of SiO2 simultaneously during a linear growth period, and wherein forming the trench layer of SiO2 on the trench wall includes forming the trench layer of SiO2 that has a thickness that is approximately 30% thicker than a thickness of the top layer of SiO2.

A method comprising:

• forming a logic device on a top surface of a silicon wafer, wherein the top surface has a (100) crystal plane orientation and wherein the logic device includes a logic gate separated from the top surface by a logic gate oxide;
• and
• forming an EEPROM (Electronically Erasable Programmable Read Only Memory) device on a trench wall of the silicon wafer, wherein the trench wall has a different order plane-orientation than the top surface and wherein the EEPROM device includes an EEPROM gate separated from the trench wall by an EEPROM gate oxide, wherein the logic gate oxide has a thickness which is different from a thickness of the EEPROM gate oxide.