Method of fabricating a gate dielectric layer for a thin film transistor

A method forming a thin film transistor, featuring a composite gate dielectric layer, on an insulating substrate, comprising the steps of:

• providing said insulating substrate;
• forming a first rough polysilicon layer on said insulating substrate;
• thermally growing a first silicon oxide layer, in a furnace, on said polysilicon layer;
• subsequent to growing said first silicon oxide layer, performing a first anneal procedure, in situ in said furnace, to improve TFT parametric performance;
• thermally depositing a second silicon oxide gate dielectric layer, on underlying, said first silicon oxide dielectric layer, via thermal decomposition of tetraethylorthosilicate (TEOS),
• performing a second anneal procedure to densify said second silicon oxide gate dielectric layer, resulting in said composite gate dielectric layer, comprised of densified, said second silicon oxide gate dielectric layer on said.first silicon oxide gate insulator layer, said composite gate dielectric layer having a thickness of from about 550 to 850 Angstroms;
• depositing a second polysilicon layer;
• patterning of said second polysilicon layer, and of said composite gate dielectric layer to create a polysilicon gate structure on said composite gate dielectric layer;
• and
• forming a source/drain region in a portion of said first polysilicon layer, not covered by said polysilicon gate structure.

A method of forming a thermally deposited, gate dielectric layer, for a thin film transistor device, comprising the steps of:

• providing an insulating substrate;
• forming a rough polysilicon layer on said insulating substrate;
• thermally depositing a silicon oxide gate dielectric layer on said polysilicon layer, using tetraethylorthosilicate as a source to a thickness of from about 500 to 700 Angstroms;
• and
• performing an anneal procedure to densify said silicon oxide gate dielectric layer.