Ferroelectric memory device and method of forming the same

A method of forming a ferroelectric memory device, the method comprising:

• preparing a semiconductor substrate including an interlayer dielectric layer;
• forming a contact plug in the interlayer dielectric layer;
• stacking a lower electrode layer covering the contact plug;
• forming a hard mask layer on the lower electrode layer;
• patterning the hard mask layer and lower electrode layer to form a cylindrical lower electrode correspondingly covering the contact plug;
• conformally stacking a ferroelectric layer substantially over the entire surface of the semiconductor substrate;
• conformally stacking an upper electrode layer over the ferroelectric layer;
• etching the upper electrode layer to form a spacer shaped upper electrode surrounding the vertical sidewalls of the lower electrode with the ferroelectric layer disposed between the upper and lower electrodes;
• stacking a conductive layer over substantially the entire semiconductor substrate;
• and
• patterning the conductive layer to form a plate line over a region of the semiconductor substrate where the upper electrode is formed, the plate line being in electrical contact with the upper electrode.

A method of forming a ferroelectric memory device comprising:

• preparing a semiconductor substrate including an interlayer dielectric layer;
• forming a matrix of contact plugs in the interlayer dielectric layer;
• forming a sacrificial oxide layer on the interlayer dielectric layer;
• forming a matrix of node holes in the sacrificial oxide layer over each of the contact plugs;
• filling the matrix of node holes with a lower electrode material by using an electroplating method;
• forming a matrix of cylindrically shaped lower electrodes over each of the contact plugs by removing the sacrificial oxide layer;
• conformally stacking a ferroelectric layer substantially over the entire surface of the semiconductor substrate;
• conformally stacking an upper electrode layer over the ferroelectric layer;
• etching the upper electrode layer to create memory cells by creating spacer shaped upper electrodes surrounding the vertical sidewalls of the lower electrodes with the ferroelectric layer disposed between the upper and lower electrodes;
• stacking a conductive layer over substantially the entire semiconductor substrate;
• and
• patterning the conductive layer to form lines connecting upper electrodes of cells composing a row or column of a memory cell matrix.