Multi-layered resist structure and manufacturing method of semiconductor device
AssigneeFujitsu Limited
InventorsAkihiko Otoguro, Satoshi Takechi
Life of this patent
Estimating the term…
Loading patent…
AssigneeFujitsu Limited
InventorsAkihiko Otoguro, Satoshi Takechi
Estimating the term…
There are provided steps of forming a lower resist layer on a patterning objective layer, forming an organic intermediate layer made of organic material, that contains no Si—O bond in its structure, on the lower resist layer, forming an upper resist layer made of alicyclic resin on the organic intermediate layer, forming a pattern by exposing/developing the upper resist layer, transferring the pattern of the upper resist layer onto the organic intermediate layer by etching the organic intermediate layer while using the upper resist layer as a mask, transferring a pattern of the organic intermediate layer onto the lower resist layer by etching the lower resist layer while using the organic intermediate layer as a mask, and etching the patterning objective layer while using the lower resist layer as a mask. Accordingly, a semiconductor device manufacturing method containing patterning steps employing a multi-layered resist structure, that is capable of suppressing deformation of the pattern of the upper resist layer formed of alicyclic compound, can be provided.
A semiconductor device manufacturing method comprising the steps of:
A semiconductor device manufacturing method comprising the steps of:
A semiconductor device manufacturing method comprising the steps of:
A semiconductor device manufacturing method comprising the steps of:
Dependencies are inferred from the claim text.