Field-assisted fusion bonding

#This invention relates to semiconductor bonding, including but not limited to fusion bonding of two or more semiconductor wafers.

#Semiconductors, such as silicon, germanium, or gallium arsenide, are utilized to build components such as Micro Electromechanical Systems (MEMS), also known as Microsystems Technology (MST), that provide various different functions in numerous different devices. For example, MEMS may be used in inkjet printers, pressure sensors, crash sensors in vehicles, accelerometers, gyros, inertial instruments, and so forth. An example of such a device is shown in FIG. 1. In this instance, two silicon-on-insulator (SOI) wafers 101 and 105 surround a center wafer 103 The device layers on each of these SOI wafers are etched to provide the appropriate function desired for the component. Two different ways of bonding semiconductor wafers are predominantly utilized: fusion bonding and anodic bonding.

#Fusion bonding is performed by hydrolyzing the surfaces of the wafers, aligning the wafers relative to each other as necessary, and contacting the wafers together. The wafers are then brought to a fusion bonding temperature, typically between 300° C. and 800° C., and subsequently annealed at a higher temperature such as 800° C. to 1100° C. to increase the bond strength.

#FIG. 1 is a cross-sectional side view of a MEMS structure.

#FIG. 2 is a cross-sectional side view of three wafers in accordance with the invention.

#FIG. 3 is a cross-sectional side view of three wafers having electrical contacts in accordance with the invention.

#The following describes an apparatus for and method of field-assisted fusion bonding. Contacts are placed at various points along different surfaces of a combination of two or more wafers. An electric field is applied to the contacts, thereby creating an electrostatic attractive force between the wafers. The temperature of the wafer combination is elevated to a fusion bonding temperature while the electric field is applied.

#The cross-sectional side view in FIG. 2 shows three wafers 201, 203, and 205 that are intended to be bonded together. Application of the present invention to various examples of different combinations of wafers will be shown. Note that the figures are not drawn to scale.

#An oxide layer 207, 209, 211, and 213, such as silicon dioxide SiO2 for silicon wafers or other oxides as appropriate to the wafer composition, is grown on each of the surfaces that will be in contact between the wafers 201, 203, and 205. Oxide layers 207, 209, 211, and 213 are grown on the surfaces to a depth of approximately 1 to 2 microns. The surfaces with grown oxide layers are hydrolyzed as known in the art.