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US 6,887,131 B2Granted
Polishing pad design
AssigneeIntel Corporation
InventorsLei Jiang, Sadasivan Shankar, Paul Fischer
Life of this patent
Estimating the term…
Abstract
A method is provided for creating a polish pad. This may involve determining a design layout of a wafer. The design layout may include a distribution of metal line features on the wafer. A polish pad design may be created/determined based on the determined layer. The polish pad may have asperities having a width greater than a width of metal line features of the wafer.
Claims7
A method comprising:
- determining a distribution of metal line features of a wafer, the distribution including a width of metal line features;
- and
- creating a polish pad having a roughness distribution based on the determined distribution of metal line features,
- wherein creating the polish pad comprises creating asperities on the polish pad having a width greater than the width of metal line features of the wafer.
1 more element
A method comprising:
- determining a line width of a plurality of dominant metal line features of a wafer;
- providing a polish pad having asperities with a width greater than the line width of the plurality of dominant metal line features of the wafer;
- and
- polishing the wafer using the polish pad.
1 more element
Dependencies are inferred from the claim text.