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AssigneeNovellus Systems, Inc.
InventorsEric G. Webb, Jonathan D. Reid, John H. Sukamto, Sesha Varadarajan, Margolita M. Pollack, Bryan L. Buckalew, Tariq Majid
Estimating the term…
A negative bias is applied to an integrated circuit wafer immersed in an electrolytic plating solution to generate a DC current. After about ten percent to sixty percent of the final layer thickness has formed in a first plating time, biasing is interrupted during short pauses during a second plating time to generate substantially zero DC current. The pauses are from about 2 milliseconds to 5 seconds long, and typically about 10 milliseconds to 500 milliseconds. Generally, about 2 pauses to 100 pauses are used, and typically about 3 pauses to 15 pauses. Generally, the DC current density during the second plating time is greater than the DC current density during the initial plating time. Typically, the integrated circuit wafer is rotated during electroplating. Preferably, the wafer is rotated at a slower rotation rate during the second plating time than during the first plating time.
A method of depositing a metal layer to a selected thickness on a semiconductor wafer, comprising:
A method of depositing a metal layer to a selected thickness on a semiconductor wafer, comprising:
A method of depositing a metal layer to a selected thickness on a semiconductor wafer, comprising:
Dependencies are inferred from the claim text.