Method for chemical-mechanical polish control in semiconductor manufacturing
AssigneeYield Dynamics, Inc.
InventorAnthony J. Toprac
Life of this patent
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Abstract
A method for planarizing the surface of a semiconductor wafer or device during manufacture. Dependencies of polish rate and substrate thickness on process parameters of downforce and polish speed, and on the characteristic product high feature area on the wafer, are explicitly defined and used to control Chemical-Mechanical Polish in Run-to-Run and real-time semiconductor production control applications.
Claims23
A method for determining critical polish time tc using a polish pad during semiconductor manufacture of a structure having one or more mesas and one or more valleys, comprising the steps of:
- obtaining the value of mask-scale or reticle mask-scale M;
- determining a pad compression spring constant k of the polish pad;
- measuring on a patterned structure high feature and low feature thicknesses at one or more identifiable locations, the first such measurement (before any polish) determining the values of ym0 (high features) and yv0 (low features);
- determining the polish recipe value for downforce Fdn pushing the structure against the polish pad;
- determining the planar structure polish rate Rp;
- and
- computing a critical polish time prior to encountering one of the valleys according to:
- t
- c
- =
- F
- d
-
-
- n
- -
- M
-
-
- k
-
-
- A
- w
-
- (
- y
- m
-
-
- o
- -
- y
- v
-
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- o
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- k
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- A
- w
-
- R
- p
- .
- [
- M1
- ]
A method for production wafer polish using a CMP Run-to-Run control model used to control production of wafer polish, comprising the steps of:
- a. initializing production on a CMP tool by determining the planar wafer polish rate Rp;
- b. measuring incoming production wafer high (ym0) and low (yv0) feature thickness at one or more identifiable locations on the wafer;
- c. determining appropriate values for M, determined by the high feature area of a specific product being polished, spring constant k of a polish pad, wafer area Aw, and Fdn, the downforce value set in the polish recipe, retrieved from a database;
- d. calculating critical time constant tc given by:
- t
- c
- =
- F
- d
-
-
- n
- -
- M
-
-
- k
-
-
- A
- w
-
- (
- y
- m
-
-
- o
- -
- y
- v
-
-
- o
- )
- k
-
-
- A
- w
-
- R
- p
- [
- M1
- ]
- e. substituting critical time constant tc into the following equation:
- y
- m
- =
- y
- m
-
-
- o
- +
- R
- p
-
- t
- c
- M
- and performing the following conditional logic:
- If ym≦Tm, where Tm is the post-polish thickness target, then use
- y
- m
- =
- y
- mo
- +
- R
- p
-
- t
- M
- [M 3]
- in Step f;
- otherwise, use
- ym=yv0+hc+Rp(t−tc)+(1−M)hc[exp(kRpAw(t−tc)/Fdn)−1] [M5];
- f. implicitly solving for polish time from Equation M3 or M5 as determined in Step e with target Tm substituted for ym;
- g. measuring post-polish ym, yv at the same locations used in Step b;
- h. implicitly solving Equation M3 or M5, as determined in Step e, for Rp using measurements from Step g;
- i. filtering the new value for Rp to produce a new estimated value of Rp to be used in Steps b through f for the next wafer or batch of wafers to be polished;
- j. determining the recipe value for polish time for the next wafer or batch of wafers to be polished by repeating the above sequence starting with Step b, above, for this next wafer or batch of wafers using the new estimated value of Rp determined in Step i, above;
- and
- k. setting the recipe value for polish time on the polish tool prior to polishing the corresponding wafer or batch of wafers.
A method for production wafer polish using a CMP real-time control model used to control production of wafer polish, comprising the steps of:
- a. determining the appropriate values for M, determined by the high feature area of a specific product being polished, spring constant k of a polish pad, wafer area Aw, and Fdn, the downforce value set in the polish recipe, retrieved from a database;
- b. implicitly solving for Rp in
- ym=yv0+hc+Rp(t−tc)+(1−M)hc[exp(kRpAw(t−tc)/Fdn)−1] [M5]
- as determined with in-situ measured thickness used for ym0 (thickness at start) and ym;
- c. implicitly solving Equation M5 for time t;
- d. comparing present polish time to the solution for polish time obtained in Step c;
- and p1 e. if actual polish time equals or exceeds the Step c polish time, then stopping wafer polish.
Dependencies are inferred from the claim text.