Parallel programming of multiple-bit-per-cell memory cells on a continuous word line

A write operation for a multiple-bit-per-cell (MBPC) non-volatile memory, comprising applying a write signal to a word line that is connected to multiple selected memory cells that are being simultaneously programmed, wherein the selected memory cells are being programmed to respective target threshold voltages that represent respective multi-bit data values being written, and the write signal includes:

• a plurality of programming cycles during which programming voltages applied to the selected memory cells change threshold voltages of the selected memory cells;
• and
• a plurality of verify cycles during which sensing operations determine whether the selected memory cells have reached the respective target threshold voltages, wherein
• the programming cycles have shorter duration at an end of a first interval than at a start of the first interval;
• increase in duration immediately after the first interval, and for a second interval that follows the first interval have shorter duration at an end of the second interval than at a start of the second interval.

A write operation for a multiple-bit-per-cell (MBPC) non-volatile memory, comprising applying a write signal to a word line that is connected to multiple selected memory cells that are being simultaneously programmed, wherein the selected memory cells are being programmed to respective target threshold voltages that represent respective multi-bit data values being written, and the write signal includes:

• a plurality of programming cycles during which programming voltages applied to the selected memory cells change threshold voltages of the selected memory cells;
• and
• a plurality of verify cycles during which sensing operations determine whether the selected memory cells have reached the respective target threshold voltages, wherein
• a programming voltage applied to the word line during the programming cycles increases in steps of different sizes during the write operation.

A write operation for a multiple-bit-per-cell (MBPC) non-volatile memory, comprising:

• performing a write operation on a selected memory cell using a first set of programming parameters for the write operation, wherein the first set of programming parameters are such that the write operation changes a threshold voltage of a typical memory cell to a target threshold voltage;
• determining whether the selected memory cell has the target threshold voltage after the write operation;
• and
• in response to the selected memory cell not having the target threshold voltage, applying additional programming to the selected memory cell, wherein the additional programming uses a second set of programming parameters that differ from the first set of programming parameters.

A multiple-bit-per-cell (MBPC) non-volatile memory, comprising:

• an array of memory cells including word lines connected to control gates of memory cells in respective rows of the array, bit lines connected to drains of memory cells in respective columns of the array, and source lines connected to memory cells in respective groups of columns of the array;
• a plurality of multilevel write circuits, each multilevel write circuit corresponding to one of the groups of the columns in the memory array;
• a column selection circuit that for a write operation connects each multilevel write circuit to a selected one of the bit lines that are connected to the drains of memory cells in one of the columns in the group corresponding to the multilevel write circuit;
• and
• a plurality of source line bias circuits respectively coupled to the source lines, wherein for the write operation, each source line bias circuit biases the source line coupled to the source line bias circuit to a voltage that depends on a multi-bit data value being written in a selected one of the memory cells coupled to that source line.

A multiple-bit-per-cell (MBPC) non-volatile memory, comprising:

• an array of memory cells including word lines connected to control gates of memory cells in respective rows of the array, bit lines connected to drains of memory cells in respective columns of the array, and source lines connected to memory cells in respective groups of columns of the array;
• a plurality of multilevel write circuits, each multilevel write circuit corresponding to one of the groups of the columns in the memory array, wherein each multilevel write circuit is isolated from the other multilevel write circuits for performing parallel write operations;
• and
• a column selection circuit that for a write operation connects each multilevel write circuit to a selected one of the bit lines that are connected to the drains of memory cells in one of the columns in the group corresponding to the multilevel write circuit.