Stacked 1T-nMTJ MRAM structure
AssigneeMicron Technology, Inc.
InventorsHasan Nejad, Mirmajid Seyyedy
Life of this patent
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Abstract
This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read multiple MRAM cells, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.
Claims7
A method of fabricating a memory device, comprising:
- providing a substrate;
- forming an access transistor on said substrate, said access transistor having a first and a second active area;
- providing a bit line in electrical contact with said access transistor at said first active area;
- providing an interconnect in electrical contact with said access transistor at said second active area;
- forming a first magnetic bit over said access transistor;
- forming a first sense line associated with said first magnetic bit, which is in electrical contact with said interconnect;
- forming a second magnetic bit over said first magnetic bit;
- and
- forming a second sense line associated with said second magnetic bit, which is in electrical contact with said interconnect.
Dependencies are inferred from the claim text.