Resistive ladder, summing node circuit, and trimming method for a subranging analog to digital converter

A differential resistive network comprising:

• positive and negative input terminals for receiving an analog differential input signal;
• a first ladder including a first plurality of serially connected resistors coupled to said positive terminal;
• a first pair of complementary current sources, including first and second current sources, for maintaining a constant current flow through said first ladder;
• a second ladder including a second plurality of serially connected resistors coupled to said negative terminal;
• and
• a second pair of complementary current sources, including third and fourth current sources, for maintaining a constant current flow through said second ladder
• wherein said pair of current sources is implemented in one of complementary bipolar technology and CMOS technology,
• wherein if the pair of current sources is implemented in bipolar technology, said pair includes a PNP current source and a NPN current source, and
• wherein if the pair of current sources is implemented in CMOS technology, said pair includes a PMOS current source and a NMOS current source.

A differential quantizer comprising:

• first and second input means for receiving a differential analog input signal;
• a first resistive ladder having a first plurality of resistors coupled in series and connected to said first input means for receiving an input signal and providing a first plurality of voltage comparison signals;
• a first pair of complementary current sources, including first and second current sources, for maintaining a constant current flow through said first resistive ladder;
• a second resistive ladder having a second plurality of resistors coupled in series and connected to said second input means for receiving an input signal and providing a second plurality of voltage comparison signals;
• a second pair of complementary current sources, including third and fourth current sources, for maintaining a constant current flow through said second resistive ladder;
• comparator means for comparing the first plurality of voltage comparison signals tapped from said first resistive ladder with said second plurality of voltage comparison signals tapped from said second resistive ladder, and
• encoding means coupled to said comparator means for providing a digital output
• wherein said first pair of current sources is implemented in one of complementary bipolar technology and CMOS technology,
• wherein if the pair of current sources is implemented in bipolar technology, said pair includes a PNP current source and a NPN current source as first and second current sources, respectively, and
• wherein if the pair of current sources is implemented in CMOS technology, said pair includes a PMOS current source and a NMOS current source as first and second current sources, respectively.

A differential quantizer comprising:

• first and second input means for receiving a differential analog input signal;
• a first resistive ladder having a first plurality of resistors coupled in series and connected to said first input means for receiving an input signal and providing a first plurality of voltage comparison signals;
• a first pair of complementary current sources, including first and second current sources, for maintaining a constant current flow through said first resistive ladder;
• a second resistive ladder having a second plurality of resistors coupled in series and connected to said second input means for receiving an input signal and providing a second plurality of voltage comparison signals;
• a second pair of complementary current sources, including third and fourth current sources, for maintaining a constant current flow through said second resistive ladder;
• comparator means for comparing the first plurality of voltage comparison signals tapped from said first resistive ladder with said second plurality of voltage comparison signals tapped from said second resistive ladder;
• and
• encoding means coupled to said comparator means for providing a digital output,
• wherein said input means are offset from said comparator means by a pair of resistors on either side of each input means, said pairs of resistors having a resistance half that of the other resistors in said first and second ladders.

A method for quantizing an analog signal including the steps of:

• receiving a differential analog input signal with a positive signal and a negative signal;
• generating a first plurality of voltage comparison signals by inputting said positive signal to a first resistive ladder having a first plurality of resistors coupled in series;
• maintaining a constant current flow through said first resistive ladder using a first pair of complementary current sources;
• generating a second plurality of voltage comparison signals by inputting said negative signal to a second resistive ladder having a second plurality of resistors coupled in series;
• maintaining a constant current flow through said second resistive ladder using a second pair of complementary current sources;
• comparing the first plurality of voltage comparison signals with said second plurality of voltage comparison signals to provide output signals;
• and
• encoding said output signals to provide a digital output,
• wherein said first pair of current sources is implemented in one of complementary bipolar technology and CMOS technology,
• wherein if the pair of current sources is implemented in bipolar technology, said pair includes a PNP current source and a NPN current source, respectively, and
• wherein if the pair of current sources is implemented in CMOS technology, said pair includes a PMOS current source and a NMOS current source.

A summing node circuit comprising:

• input means for receiving an input signal;
• a pair of complementary digital to analog converters (DACs) for generating a reconstruction signal;
• and
• summing means for subtracting said reconstruction signal from said input signal to produce a residue signal,
• wherein said input signal is a differential signal.

A subranging analog to digital converter (ADC) comprising:

• input means for receiving an analog input signal;
• a coarse pass circuit including:
• a sample and hold circuit for generating a sampled signal from said input signal;
• a coarse quantizer for generating a first digital word from said sampled signal;
• and
• a summing node circuit including a pair of complementary DACs for generating an analog reconstruction signal of said first digital word and a summing amplifier for subtracting said reconstruction signal from said sampled input signal to produce a residue signal;
• a fine pass circuit including a fine quantizer for generating a second digital word from said residue signal;
• and
• digital correction means for combining said first and second digital words to generate a digital output.

A method for generating a residue signal from an analog input signal and a quantizer output in a subranging ADC including the steps of:

• receiving said input signal;
• generating a reconstruction signal from said quantizer output using a pair of complementary DACs;
• and
• subtracting said reconstruction signal from said input signal to produce a residue signal,
• wherein said input signal is a differential signal.

A method for trimming a subranging ADC, said ADC comprising a coarse quantizer that quantizes an input signal and provides a first digital word, a pair of complementary DACs that generate a reconstruction of said first digital word, a summing amplifier that subtracts said reconstruction from said input signal to produce a residue signal, and a fine quantizer that quantizes said residue signal and provides a second digital word that is combined with said first digital word to form an output word, said method including the steps of:

• trimming each of the DAC cells on one of the complementary DACs;
• after the DAC cells are trimmed, trimming the overall DAC gain to match the gain of the coarse quantizer;
• and
• trimming the gain of the fine quantizer to match one quantization Q level of the previous subranged stage.