Apparatus for dynamically repairing a semiconductor memory
AssigneeMicron Technology, Inc.
InventorsBrian P. Callaway, Aaron M. Baum
Life of this patent
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Abstract
An architecture for dynamically repairing a semiconductor memory, such as a Dynamic Random Access Memory (DRAM), includes circuitry for dynamically storing memory element remapping information. Memory is tested for errors by writing, then reading a plurality of memory blocks, such as rows or columns, in parallel. Memory is dynamically reprogrammed in order to remap unused spare memory elements for failed memory elements when errors are detected. Unused spare memory elements are remapped utilizing a circuit that overrides unblown fuses or antifuses.
Claims29
A semiconductor memory including a capability for testing for memory faults, comprising:
- a first memory block comprising a first plurality of bits of memory;
- a second memory block comprising a second plurality of bits of memory;
- a circuit for writing a pattern of bits to the first memory block;
- a circuit for writing the pattern of bits to the second memory block;
- a circuit for reading the first plurality of bits of memory from the first memory block as a first plurality of read bits;
- a circuit for reading the second plurality of bits of memory from the second memory block as a second plurality of read bits;
- and
- a circuit for comparing each one of the first plurality of read bits with a corresponding one of the second plurality of read bits.
A memory including a capability for repairing a faulty memory block by selecting a spare memory block to logically replace the faulty memory block, comprising:
- a spare memory block comprising a plurality of memory bits;
- a plurality of address bits for controlling a mapping of the spare memory block to replace the faulty memory block, wherein a spare memory address bit is one of the plurality of address bits;
- a circuit for permanently activating the spare memory address bit;
- and
- a circuit for temporarily activating the spare memory address bit, wherein the spare memory address bit is activated when the spare memory address bit is either permanently activated or temporarily activated.
A circuit for repairing a memory with a faulty memory block by selecting a spare memory block to logically replace the faulty memory block, comprising:
- a permanent memory for permanently selecting an address bit for the spare memory block;
- and
- a gate for temporarily activating the address bit for the spare memory block, wherein the address bit for the spare memory block is activated when the address bit is either permanently activated or temporarily activated.
A circuit for repairing a memory with a faulty memory block by selecting a spare memory block to logically replace the faulty memory block, comprising:
- a permanent memory element having an output that when activated permanently activates an address bit for the spare memory block;
- a transistor having a gate and an output that when asserted temporarily activates the address bit for the spare memory block;
- and
- a latching memory element having an input coupled to the output of the permanent memory element and to the output of the transistor, an output, and an enable, the latching memory element being configured to latch an asserted value when either the output of the permanent memory element is being asserted or the output of the transistor is being asserted when the enable of the latching memory element is asserted.
A memory including a capability for testing for and repairing memory faults comprising:
- a first memory block comprising a first plurality of bits of memory;
- a second memory block comprising a second plurality of bits of memory;
- a spare memory block comprising a spare plurality of bits of memory;
- a circuit for writing a pattern of bits to the first memory block;
- a circuit for writing the pattern of bits to the second memory block;
- a circuit for reading the first plurality of bits of memory from the first memory block as a first plurality of read bits;
- a circuit for reading the second plurality of bits of memory from the second memory block as a second plurality of read bits;
- a circuit for comparing each one of the first plurality of read bits with a corresponding one of the second plurality of read bits;
- a circuit for identifying the first memory block as a faulty memory block when at least one of the first plurality of read bits differs from a corresponding one of the second plurality of read bits;
- a plurality of address bits for controlling a mapping of the spare memory block to replace the faulty memory block;
- a spare memory address bit is one of the plurality of address bits;
- a circuit for permanently activating the spare memory address bit;
- and
- a circuit for temporarily activating the spare memory address bit that is coupled to and responsive to the circuit for identifying the first memory block as the faulty memory block, wherein the spare memory address bit is activated when the spare memory address bit is either permanently activated or temporarily activated.
A memory including a capability for dynamically testing and repairing itself, comprising:
- a plurality of blocks of memory;
- a circuit for testing at least two of the plurality of blocks of memory to identify a first faulty memory block;
- a circuit for identifying a spare memory block from the plurality of blocks of memory that has not been permanently remapped and that has not been temporarily remapped to replace a second faulty memory block;
- and
- a circuit for temporarily remapping the spare memory block to replace the first faulty memory block.
An electronic system, comprising:
- an input device;
- an output device;
- a processor device in communication with the input device and the output device;
- and
- a memory in communication with the processor device, comprising:
- a plurality of blocks of memory;
- a circuit for testing at least two of the plurality of blocks of memory to identify a first faulty memory block;
- a circuit for identifying a spare memory block from the plurality of blocks of memory that has not been permanently remapped and that has not been temporarily remapped to replace a second faulty memory block;
- and
- a circuit for temporarily remapping the spare memory block to replace the first faulty memory block.
Dependencies are inferred from the claim text.