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US 6,877,079 B2Granted
Memory system having point-to-point bus configuration
AssigneeSamsung Electronics Co., Ltd.
InventorsChang-sik Yoo, Kye-hyun Kyung
Life of this patent
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Abstract
A clocking system and method in a point-to-point bus configuration overcomes the limitations of conventional approaches. In one embodiment, the present invention ensures the same phase relationship for the write clock in the write direction for all data transfers between modules, and similarly the same phase relationship for the read clock in the read direction for all data transfers between modules, regardless of module location. In another embodiment, on a given module, all transfers of data between a data buffer and a memory device in both read and write directions are clocked by a read clock signal and a write clock signal that have the same phase relationship and have the same propagation delay as the data bus between the buffer and the memory device.
Claims39
A memory module for use in a memory system, the memory module comprising:
- a first memory module including a memory device, a first buffer, and a second buffer, the first buffer receiving a first write clock signal and a control signal that includes a read or write command in a first direction of transmission, the second buffer receiving the first write clock signal in the first direction of transmission and a first read clock signal in a second direction of transmission, the second buffer being coupled to a first data bus and a second data bus;
- the first memory module generating a second write clock signal in response to, and in phase with, the first write clock signal, for transmitting data from the second buffer in the first direction of transmission if the write command indicates that data is to be written to a second memory module in the memory system, the first read clock signal and the second write clock signal being transmitted over independent signal lines, and generating a memory write clock signal in response to, and in phase with, the first write clock signal, for writing data from the second buffer to the memory device if the write command indicates that data is to be written to the memory device in the first memory module;
- and
- the first memory module generating a memory read clock signal in response to, and in phase with, a memory write clock signal, for reading data from the memory device to the second buffer if the read command indicates that data is to be read from the memory device in the first memory module, the memory write clock signal having substantially the same propagation delay as data transferred from the second buffer to the memory device and the memory read clock signal having substantially the same propagation delay as data transferred from the memory device to the second buffer.
1 more element
A memory module for use in a memory system, the memory module comprising:
- a first memory module including a memory device and a buffer, the buffer receiving a first write clock signal and a control signal that includes a read or write command in a first direction of transmission, the buffer receiving a first read clock signal in a second direction of transmission, the buffer being coupled to a first data bus and a second data bus;
- the first memory module generating a second write clock signal for timing the transmission of data in the first direction of transmission on the second data bus, the first read clock signal and the second write clock signal being transmitted over independent signal lines;
- and
- the first memory module generating a memory write clock signal in response to, and in phase with, the first write clock signal, for writing data from the buffer to the memory device if the write command indicates that data is to be written to the memory device in the first module, the memory write clock signal having substantially the same propagation delay as data transferred from the buffer to the memory device.
1 more element
A memory module for use in a memory system, the memory module comprising:
- a first memory module including a memory device and a buffer, the buffer receiving a first write clock signal and a control signal that includes a read or write command in a first direction of transmission, the buffer receiving a first read clock signal in a second direction of transmission, the buffer being coupled to a first data bus and a second data bus;
- the first memory module generating a second write clock signal for timing the transmission of data in the first direction of transmission on the second data bus, the first read clock signal and the second write clock signal being transmitted over independent signal lines;
- and
- the first memory module generating a memory read clock signal in response to, and in phase with, a memory write clock signal, for reading data from the memory device to the buffer if the read command indicates that data is to be read from the memory device in the first memory module the memory read clock signal having substantially the same propagation delay as data transferred from the memory device to the buffer;
- the memory write clock signal being generated in response to, and in phase with, the first write clock signal.
2 more elements
A memory module for use in a memory system, the memory module comprising:
- a first memory module including a memory device and a buffer, the buffer receiving a first write clock signal and a control signal that includes a read or write command in a first direction of transmission, the buffer receiving a first read clock signal in a second direction of transmission, the buffer being coupled to a first data bus and a second data bus;
- and
- the first memory module generating a second read clock signal in response to, and in phase with, the first write clock signal, for transmitting data from the buffer in the second direction of transmission if the read command indicates that data is to be read from a second memory module in the memory system, wherein the first write clock signal and the second read clock signal are transmitted over independent signal lines.
A memory system comprising:
- a memory controller for generating a first write clock signal and a control signal that includes a read or write command;
- and
- a first memory module including a memory device and a buffer, the buffer receiving the first write clock signal and the control signal in a first direction of transmission, the buffer receiving a first read clock signal in a second direction of transmission, the buffer being coupled to a first data bus and a second data bus;
- the first memory module generating a second write clock signal in response to, and in phase with, the first write clock signal, for transmitting data from the buffer in the first direction of transmission if the write command indicates that data is to be written to a second memory module in the memory system, the first read clock signal and the second write clock signal being transmitted over independent signal lines, and generating a memory write clock signal in response to, and in phase with, the first write clock signal for writing data from the buffer to the memory device if the write command indicates that data is to be written to the memory device in the first memory module;
- and
- the first memory module generating a memory read clock signal in response to, and in phase with, the memory write clock signal for reading data from the memory device to the buffer if the read command indicates that data is to be read from the memory device in the first memory module, the memory write clock signal having substantially the same propagation delay as data transferred from the buffer to the memory device and the memory read clock signal having substantially the same propagation delay as data transferred from the memory device to the buffer.
3 more elements
A memory system comprising:
- a memory controller for generating a first write clock signal and a control signal that includes a read or write command;
- a read clock generator for generating a first read clock signal;
- and
- a first memory module including a memory device and a buffer, the buffer receiving the first write clock signal and the control signal in a first direction of transmission, the buffer receiving the first read clock signal in a second direction of transmission, the buffer being coupled to a first data bus and a second data bus;
- the first memory module generating a second write clock signal in response to, and in phase with, the first write clock signal, for transmitting data from the buffer in the first direction of transmission if the write command indicates that data is to be written to a second memory module in the memory system, the first read clock signal and the second write clock signal being transmitted over independent signal lines, and generating a memory write clock signal in response to, and in phase with, the first write clock signal, for writing data from the buffer to the memory device if the write command indicates that data is to be written to the memory device in the first memory module;
- the first memory module generating a memory read clock signal in response to, and in phase with, the memory write clock signal, for reading data from the memory to the buffer if the read command indicates that data is to be read from the memory device in the first memory module, the memory write clock signal having substantially the same propagation delay as data transferred from the buffer to the memory device and the memory read clock signal having substantially the same propagation delay as data transferred from the memory device to the buffer;
- and
- the first memory module generating a second read clock signal in response to, and in phase with, the first read clock signal, for transmitting data from the buffer in the second direction of transmission.
5 more elements
A method for generating clock signals in a memory system comprising:
- receiving, at a first buffer on a first memory module, a first write clock signal and a control signal that includes a read or write command in a first direction of transmission, the first memory module including a memory device;
- receiving, at a second buffer on the first memory module, the first write clock signal in the first direction of transmission and a first read clock signal in a second direction of transmission, the second buffer being coupled to a first data bus and a second data bus;
- generating a second write clock signal in response to, and in phase with, the first write clock signal, for transmitting data from the second buffer in the first direction of transmission if the write command indicates that data is to be written to a second memory module in the memory system, the first read clock signal and the second write clock signal being transmitted over independent signal lines, and generating a memory write clock signal in response to, and in phase with, the first write clock signal, for writing data from the second buffer to the memory device if the write command indicates that data is to be written to the memory device in the first memory module;
- and
- generating a memory read clock signal in response to, and in phase with, a memory write clock signal, for reading data from the memory device to the second buffer if the read command indicates that data is to be read from the memory device in the first memory module, the memory write clock signal having substantially the same propagation delay as data transferred from the second buffer to the memory device and the memory read clock signal having substantially the same propagation delay as data transferred from the memory device to the second buffer.
2 more elements
A method for generating a clock signal in a memory system comprising:
- receiving, at a buffer on a first memory module, a first write clock signal and a control signal that includes a read or write command in a first direction of transmission, the first memory module including a memory device;
- receiving a first read clock signal in a second direction of transmission, the buffer being coupled to a first data bus and a second data bus, and generating a second write clock signal for timing the transmission of data in the first direction of transmission on the second data bus, the first read clock signal and the second write clock signal being transmitted over independent signal lines;
- and
- generating a memory write clock signal in response to, and in phase with, the first write clock signal, for writing data from the buffer to the memory device if the write command indicates that data is to be written to the memory device in the first memory module, the memory write clock signal having substantially the same propagation delay as data transferred from the buffer to the memory device.
1 more element
A method for generating a clock signal in a memory system comprising:
- receiving, at a buffer on a first memory module, a first write clock signal and a control signal that includes a read or write command in a first direction of transmission, the first memory module including a memory device;
- receiving a first read clock signal in a second direction of transmission, the buffer being coupled to a first data bus and a second data bus, and generating a second write clock signal for timing the transmission of data in the first direction of transmission on the second data bus, the first read clock signal and the second write clock signal being transmitted over independent signal lines;
- generating, in response to the first write clock signal, a memory write clock signal, the memory write clock signal being in phase with the first write clock signal;
- and
- generating a memory read clock signal in response to, and in phase with, the memory write clock signal, for reading data from the memory device to the buffer if the read command indicates that data is to be read from the memory device in the first memory module, the memory read clock signal having substantially the same propagation delay as data transferred from the memory device to the buffer.
2 more elements
A method for generating a clock signal in a memory system comprising:
- receiving, at a buffer on a first memory module, a first write clock signal and a control signal that includes a read or write command in a first direction of transmission, the first memory module including a memory device;
- receiving a first read clock signal in a second direction of transmission, the buffer being coupled to a first data bus and a second data bus;
- and
- generating a second read clock signal in response to, and in phase with, the first write clock signal, for transmitting data from the buffer in the second direction of transmission if the read command indicates that data is to be read from a second memory module in the memory system, wherein the first write clock signal and the second read clock signal are transmitted over independent signal lines.
1 more element
Dependencies are inferred from the claim text.