# US 6,875,624 B2 · Combined E-beam and optical exposure semiconductor lithography

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- Number: US 6,875,624 B2
- Document ID: US6875624B2
- Status: Granted
- Kind: B2
- Application number: 10/141,614
- Filed: 2002-05-08
- Published: 2003-11-13
- Granted: 2005-04-05
- Earliest claimed: 2002-05-08
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chin-Hsiang Lin
- Web page: https://patentgrep.com/patent/US6875624B2

## CPC

- G03F 7/2022: {Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- B82Y 40/00: Manufacture or treatment of nanostructures
- G03F 7/7045: {Hybrid exposures, i.e. multiple exposures of the same area using different types of exposure apparatus, e.g. combining projection, proximity, direct write, interferometric, UV, x-ray or particle beam}
- H01J 37/3174: {Particle-beam lithography, e.g. electron beam lithography}
- H10P 76/2041: {Photolithographic processes}
- H10P 76/2045: {Electron beam lithography processes}
- H01J 2237/31757: hybrid, i.e. charged particles and light, X-rays, plasma
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Combined e-beam and optical exposure lithography for semiconductor fabrication is disclosed. E-beam direct writing to is employed to create critical dimension (CD) areas of a semiconductor design on a semiconductor wafer. Optical exposure lithography is employed to create non-CD areas of the semiconductor design on the semiconductor CD's of the semiconductor design can also be separated from non-CD's of the semiconductor design prior to employing e-beam direct writing and optical exposure lithography.

## Claims

### Claim 1

A method for fabricating one or more semiconductor devices according to a semiconductor design on a semiconductor wafer comprising:
coating the semiconductor wafer with photoresist;
producing a common alignment mark on the photoresist coating the semiconductor wafer for use in both e-beam direct writing and optical exposure lithography;
creating critical dimension (CD) areas of the semiconductor design on the semiconductor wafer with electron (e-) beam direct writing, the CD areas including CD's that are geometries and spacings used to monitor pattern size and ensure that the pattern size is within specification; and,
creating non-CD areas of the semiconductor design on the semiconductor with optical exposure lithography.

### Claim 2 (depends on 1)

The method of claim 1, wherein e-beam direct writing comprises e-beam direct writing the CD areas on the photoresist coating the semiconductor wafer.

### Claim 3 (depends on 1)

The method of claim 1, wherein optical exposure lithography comprises:
aligning a photomask having the non-CD areas of the semiconductor design over the photoresist coating the semiconductor wafer; and,
exposing the photoresist coating the semiconductor wafer with a light source through the photomask.

### Claim 4 (depends on 1)

The method of claim 1, further comprising developing the photoresist coating the semiconductor wafer to partially remove the photoresist in accordance with the semiconductor design.

### Claim 5 (depends on 4)

The method of claim 4, wherein the photoresist is sensitive to both e-beam direct writing and optical exposure lithography using a same developer to partially move the photoresist.

### Claim 6 (depends on 1)

The method of claim 1, wherein the photoresist is one of positive photoresist and negative photoresist.

### Claim 7 (depends on 1)

The method of claim 1, wherein optical exposure lithography comprising using stepper and scanner semiconductor photolithographic equipment.

### Claim 8 (depends on 1)

The method of claim 1, wherein e-beam writing comprises one of scanner e-beam writing and vector e-beam writing.

### Claim 9 (depends on 1)

The method of claim 1, further initially comprising separating the CD's areas of the semiconductor design on a first layer from the non-CD areas of the semiconductor design on a second layer by applying a CD rule governing which of a plurality of dimensions of the semiconductor design are the CD's.

### Claim 10 (depends on 1)

The method of claim 1, further initially comprising defining the CD's areas of the semiconductor design on a first layer as gate-shrink polysilicon areas of polysilicon gate layers of the semiconductor design, and defining the non-CD areas of the semiconductor design on a second layer as non-gate shrink polysilicon areas of the polysilicon gate layers.