Memory cell constructions comprising integrated bipolar and FET devices
AssigneeMicron Technology, Inc.
InventorArup Bhattacharyya
Life of this patent
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Abstract
The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.
Claims23
A memory cell construction, comprising:
- an electrically insulative material;
- a first crystalline layer over the electrically insulative material, the first crystalline layer comprising silicon and germanium and having a relaxed crystalline lattice;
- a second crystalline layer over the first crystalline layer, the second crystalline layer comprising a strained crystalline lattice;
- a field effect transistor comprising a gate over the second crystalline layer and an active region extending into the first crystalline layer, the active region of the field effect transistor including a pair of source/drain regions;
- and
- a bipolar transistor having a collector region, emitter region and base region;
- the base region electrically connecting with one of the source/drain regions.
A memory cell construction, comprising:
- an electrically insulative material;
- a first crystalline Si/Ge layer over the electrically insulative material;
- the first crystalline Si/Ge layer having a relaxed crystalline lattice;
- a second crystalline Si/Ge layer over the first crystalline Si/Ge layer;
- the second crystalline Si/Ge layer having a strained crystalline lattice;
- a field effect transistor comprising a gate over the second crystalline Si/Ge layer and an active region extending into the first and second crystalline Si/Ge layers, the active region of the field effect transistor including a pair of source/drain regions;
- the active region within the first Si/Ge layer being within a single crystal of the first Si/Ge layer;
- and
- a bipolar transistor having a collector region, emitter region and base region;
- the base region electrically connecting with one of the source/drain regions;
- an entirety of the collector region and emitter region being above the field effect transistor gate.
Dependencies are inferred from the claim text.