Adaptive scheduling of function cells in dynamic reconfigurable logic
AssigneeIntel Corporation
InventorJin-sheng Shyr
Life of this patent
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Abstract
Embodiments of adaptive scheduling of function calls in dynamic reconfiguration logic are generally disclosed herein. In this regard, accordance with but one example embodiment, a method of scheduling function calls in a software program in a dynamically reconfigurable computing system which includes an embedded processor and a finite number of reconfigurable logic partitions which are each programmed by a set of configuration bits dynamically loaded into the system's configuration memory is disclosed.
Claims33
A method of scheduling function calls in a software program in a dynamically reconfigurable computing system which includes an embedded processor and a finite number of reconfigurable logic partitions which are each programmed by a set of configuration bits dynamically loaded into the system's configuration memory, the method comprising the steps of:
- a) processing each function call identified within the software program into both a hard implementation for hard execution in said reconfigurable logic partitions wherein a set of configuration bits associated with said each function call is generated and into a soft execution in said embedded processor;
- b) assigning each set of said configuration bits generated during said hard implementation to a virtual partition;
- c) constructing a call history model including statistical data characterizing the patterns in calling sequence of each function call in said software program obtained from benchmark data and initially using the call history model upon invocation of said software program;
- d) employing a hierarchy of storage devices to form a pyramid of staging slots for the purpose of storing and moving each virtual partition from its initial memory location in said hierarchy of storage devices having the longest associated access latency to said configuration memory on a “time-of-need” basis;
- e) constructing a virtual partition table of statistical data to track and allocate said staging slots for the purpose of staging said virtual partitions within said pyramid, wherein prior to execution of said software program all virtual partitions are assigned to staging slots having said longest associated access latency, and wherein, while executing said software program, virtual partitions are moved to staging slots within said pyramid having either shorter or longer access latencies on said “time-of-need” basis dependent on said statistical data within said virtual partition table;
- f) upon the invocation of a current function call while executing the software program, activating hard implementation of said current function call if its associated virtual partition is located within said pyramid in a position ready for activation, otherwise activating soft implementation of said function call;
- g) during activation of the current function call, utilizing said call history model to determine probably next function calls to follow the current function call;
- h) during activation of the current function call, simultaneously initiating dynamic scheduling tasks to facilitate said staging of said virtual partitions through the hierarchy of storage devices dependent on said patterns in call sequence indicated in said call history model;
- i) upon the completion of activation of the current function call, dynamically updating said statistical data associated with the current function call in said call history model using statistical data obtained during the execution of the current function call;
- j) repeating steps (f) to (i) for said each function call until termination of execution of said software program.
A method comprising:
- analyzing a computer software program to identify subset(s) of the computer software program that could be implemented by (re)configuring reconfigurable logic to perform the identified subsets in hardware in a dynamically reconfigurable logic device;
- and
- selectively (re)configuring the reconfigurable logic within the reconfigurable logic device during run-time of the software program to implement one or more of the identified subset(s) of the computer software program.
A dynamically reconfigurable logic device comprising:
- one or more embedded controllers;
- and
- one or more reconfigurable logic element(s), communicatively coupled with at least a subset of the one or more embedded controllers, the logic device to analyze a software program to schedule function calls, wherein select function calls are selected for hard implementation through (re)configuration of at least a subset of the one or more reconfigurable logic element(s) while other function call(s) are implemented in software by one or more of the embedded controller(s), and wherein the determination of whether a function call is implemented in hardware or software is made at runtime of the software program.
Dependencies are inferred from the claim text.