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US 6,864,710 B1Granted
Programmable logic device
AssigneeCypress Semiconductor Corporation
InventorsTimothy M. Lacey, David L. Johnson
Life of this patent
Estimating the term…
Abstract
A programmable logic device comprising one or more horizontal routing channels, one or more vertical routing channels, and a logic element. Each logic element may be configured to connect between one of the horizontal routing channels and one of the vertical routing channels. The logic element may comprise a logic block cluster and a memory block.
Claims32
A programmable logic device comprising:
- one or more horizontal routing channels;
- one or more vertical routing channels;
- one or more logic elements each configured to (i) receive one or more inputs from one of said horizontal routing channels and one of said vertical routing channels and (ii) present one or more outputs to said horizontal routing channel and said vertical routing channel, wherein each of said logic elements comprises (i) a logic block array and (ii) an interconnect matrix coupled to said logic block array, said horizontal routing channel and said vertical routing channel, and
- a memory block configured to (i) receive one or more inputs from and (ii) present one or more outputs to either (a) said interconnect matrix or (b) said horizontal routing channel and said vertical routing channel.
1 more element
A programmable logic device comprising:
- a plurality of horizontal routing channels;
- a plurality of vertical routing channels;
- a plurality of first memory blocks;
- and
- a plurality of logic block arrays, wherein each of said plurality of first memory blocks and each of said plurality of logic block arrays is configured to (i) receive one or more inputs from one of said plurality of horizontal routing channels and one of said plurality of vertical routing channels and (ii) present one or more outputs to said horizontal routing channel and said vertical routing channel.
2 more elements
Dependencies are inferred from the claim text.