Adjustable differential input and output drivers

An integrated circuit common-mode-voltage bias circuit on an integrated circuit that produces an output signal at an output terminal that is used in adjusting a common-mode voltage level associated with differential data signals passing through a differential driver on the integrated circuit, the bias circuit comprising:

• a reference section that produces a reference current;
• a plurality of current mirror transistors arranged in a plurality of current mirror branch sections, each current mirror branch section having an associated current level that is a multiple of the reference current;
• a plurality of resistors, each resistor being coupled to one of the current mirror transistors;
• control transistors that switch the current mirror transistors and resistors into or out of the bias circuit to adjust the output signal produced at the output terminal;
• and
• a plurality of programmable random-access memory cells that produce static control signals, wherein the control transistors are each coupled to one of the programmable random-access memory cells and are turned on or off by the static control signals.

An integrated circuit common-mode-voltage bias circuit on an integrated circuit that produces an output signal at an output terminal that is used in adjusting a common-mode voltage level associated with differential data signals passing through a differential driver on the integrated circuit, wherein the integrated circuit includes dynamic control circuitry, the bias circuit comprising:

• a reference section that produces a reference current;
• a plurality of current mirror transistors arranged in a plurality of current mirror branch sections, each current mirror branch section having an associated current level that is a multiple of the reference current;
• a plurality of resistors, each resistor being coupled to one of the current mirror transistors;
• and
• control transistors that switch the current mirror transistors and resistors into or out of the bias circuit to adjust the output signal produced at the output terminal, wherein the control transistors receive dynamic control signals from the dynamic control circuitry on the integrated circuit and wherein the dynamic control signals turn the control transistors on and off.

A method of using first and second programmable logic device integrated circuits of a single given type in AC-coupled and DC-coupled differential communications environments, wherein each programmable logic device integrated circuit of the given type has a differential driver that is used to communicate over a differential communications link and has common-mode-voltage bias circuitry for making common-mode-voltage adjustments at the differential driver, the method comprising:

• in an AC-coupled environment in which the differential communications link has DC-blocking capacitors:
• using a first programmable logic device integrated circuit of the given type to communicate with another integrated circuit over the differential communications link;
• and
• using the common-mode-voltage bias circuitry in the first programmable logic device to make common-mode-voltage adjustments at the differential driver in the first programmable logic device integrated circuit that optimize the performance of that differential driver without regard to what common-mode voltage is desired for the other integrated circuit;
• in a DC-coupled environment in which the differential communications link has no DC-blocking capacitors:
• using a second programmable logic device integrated circuit of the same given type to communicate over the differential communication link with an additional integrated circuit;
• and
• using the common-mode-voltage bias circuitry in the second programmable logic device to make common-mode-voltage adjustments at the differential driver in the second programmable logic device while taking into account which common-mode-voltage changes result at the additional integrated circuit due to the common-mode-voltage adjustments made by the common-mode-voltage bias circuitry of the second programmable logic device.