Turbo code encoder having an improved interleaver
AssigneeInterDigital Technology Corporation
InventorSung-Hyuk Shin
Life of this patent
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Abstract
A turbo code encoder with an interleaver having two recursive systematic constituent code (RSC) encoders. The encoder encodes a finite sequence of informative bits without requiring a plurality of tail bits to flush the registers of each encoder to an all-zero state. The interleaver reduces the turbo code overhead by using only a single tail bit sequence. The interleaver also selectively reorders integers in accordance with a predefined set of rules.
Claims13
A turbo code encoder for encoding at least one input set of N ordered permutation integers I(k), where k=1 to N, comprising:
- a first encoder with memory size m, having a first input, coupled to a first source and a common source, and a multi-state register having 2m states, for receiving said input bit set as said first source and encoding said input bit set to provide an encoded input bit set at a first output;
- a hybrid S-random interleaver for receiving said input bit set and reordering the bits within said input bit set to provide a reordered input bit set, where S is an arbitrary predetermined value;
- a second encoder with memory size m, having a second input, coupled to a second source and said common source, and a multi-state register having 2m states, for receiving said reordered input bit set as said second source and encoding said reordered input bit set to provide a reordered encoded input bit set at a second output;
- and
- a switch, for switching said first encoder from said first source to said common source and for switching said second encoder from said second source to said common source;
- whereby said first output provides said common source;
- whereby said interleaver reorders said integers such that once reordered, the value for |I(k)−I(k−nL)| is not evenly divisible by L, where L=2m−1, and n is a positive integer subject to k−nL≧0 and nL≦S.
A transmitter having a turbo code encoder for encoding at least one input set of N ordered permutation integers I(k) prior to transmission, where k=1 to N, comprising:
- a first encoder with memory size m, having a first input, coupled to a first source and a common source, and a multi-state register having 2m states, for receiving said input bit set as said first source and encoding said input bit set to provide an encoded input bit set at a first output;
- an S-random interleaver for receiving said input bit set and reordering the bits within said input bit set to provide a reordered input bit set, where S is an arbitrary predetermined value;
- a second encoder with memory size m, having a second input, coupled to a second source and said common source, and a multi-state register having 2m states, for receiving said reordered input bit set as said second source and encoding said reordered input bit set to provide a reordered encoded input bit set at a second output;
- and
- a switch, for switching said first encoder from said first source to said common source and for switching said second encoder from said second source to said common source;
- whereby said first output provides said common source;
- whereby said interleaver reorders said integers such that once reordered, the value for |I(k)−I(k−nL) is not evenly divisible by L, where L=2m−1, and n is a positive integer subject to k−nL≧0 and nL≦S.
A turbo code encoder for encoding at least one input set of N ordered permutation integers I(k), where k=1 to N, comprising:
- a first encoder with memory size m, having a first input, coupled to a first source and a common source, and a multi-state register having 2m states, for receiving said input bit set as said first source and encoding said input bit set to provide an encoded input bit set at a first output;
- an interleaver for receiving said input bit set and reordering the bits within said input bit set to provide a reordered input bit set;
- a second encoder with memory size m, having a second input, coupled to a second source and said common source, and a multi-state register having 2m states, for receiving said reordered input bit set as said second source and encoding said reordered input bit set to provide a reordered encoded input bit set at a second output;
- and
- a switch, for switching said first encoder from said first source to said common source and for switching said second encoder from said second source to said common source;
- whereby said first output provides said common source;
- whereby said interleaver reorders said integers such that once reordered, the value for |I(k)−I(k−nL)| is not evenly divisible by L, where L=2m−1, n is a positive integer subject to k−nL≧0 and nL≦S, and S is an arbitrary predetermined value.
Dependencies are inferred from the claim text.