Logical fuzzy union and intersection operation calculation circuit
AssigneeSTMicroelectronics S.r.l.
InventorsFrancesco Pappalardo, Biagio Giacalone, Francesco Mammoliti, Edmondo Gangi
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AssigneeSTMicroelectronics S.r.l.
InventorsFrancesco Pappalardo, Biagio Giacalone, Francesco Mammoliti, Edmondo Gangi
Estimating the term…
The calculation circuit comprises a subtracter having a first and a second input receiving a first and, respectively, a second input datum; a first output supplying a first output datum equal to the difference between the first and the second input datum; and a second output supplying a sign flag indicating the sign of the first output datum; an XOR logic gate having a first input receiving the sign flag, a second input receiving a first logic selection signal assuming a first level for the selection of the logical fuzzy union operation and a second level for the selection of the logical fuzzy intersection operation, and an output supplying a second logic selection signal; and a multiplexer having a first and a second datum input receiving the first and, respectively, the second input datum; a selection input receiving the second selection signal; and an output supplying a second output datum constituted by the first or the second input datum (A, B) as a function of the level assumed by the second selection signal.
A calculation circuit for calculating logical fuzzy union and intersection operations, comprising:
A calculation circuit for selectively calculating fuzzy and non-fuzzy logical operations, comprising:
A method of performing logical fuzzy union and intersection operations on first and second inputs, the method being practiced on a computer, the method comprising:
Dependencies are inferred from the claim text.