One transistor DRAM cell structure and method for forming

#The present invention relates to dynamic random access memory (DRAM) cells, and more particularly to DRAM cells not requiring a separate capacitor.

#DRAMs in general have enjoyed great success primarily due to the high density with good speed. In the quest for even higher density, a technique for single transistor DRAMs has been developed. The individual cell is provided in a semiconductor on insulator (SOI) substrate and requires only a single transistor, doing away with the need for the capacitor that has historically been used in DRAMs. These types of DRAM cells are also known as capacitorless DRAM cells because of not requiring a capacitor. In such a single transistor DRAM cell, the body of the transistor is left floating and, because it is on an SOI substrate so that the bodies of the transistors are isolated from each other, charge is accumulated in the body. This alters the threshold of the transistor, and such difference can be detected.

#The technique for writing is, for N channel transistors that is the typical case, to generate holes that remain trapped in the body of the transistor, which is electrically floating. This is achieved by selecting the gate voltage so that the transistor operates to achieve greater hole/electron pair generation than removal of the holes. For erasing, the holes are removed also by adjusting the gate voltage so that hole removal occurs faster than hole/electron pair generation. One of the difficulties has been in achieving both writing and erasing with sufficient speed. If the hole removal is not sufficiently faster than hole/electron pair generation in the erase mode, then erase is too slow. Similarly, if in the write mode the hole/electron generation is not sufficiently faster than the hole removal, the write is too slow. This has been the problem, getting sufficient speed for both read and write. Thus, there is a need to find a technique for achieving sufficient speed for both read and write.

#FIGS. 1-4 illustrate sequential cross sectional views of a semiconductor device made in accordance with one embodiment of the present invention;

#FIGS. 5-9 illustrate sequential cross sectional views of a similar device structure made in accordance with a second embodiment of the present invention; and

#FIGS. 10-13 illustrate sequential cross sectional views of a similar device structure made in accordance with a third embodiment of the present invention.

#In one embodiment, a single transistor DRAM cell is a transistor formed in a SOI substrate so that the DRAM cells are formed in bodies electrically isolated from each other. Each cell has doped regions that act as source and drain contacts. Adjacent to one of the source and drain contacts and to the body is a region of the same conductivity type as the body but of a higher concentration. Also adjacent to one of the source and drain contacts and to the body is a region of the same conductivity type as the source and drain contacts but of a lower concentration. This is better understood with reference to the drawings and the following description.

#Shown in FIG. 1 is a device structure 10 formed in a SOI substrate comprising a substrate 12, an insulator 14 on substrate 12, a body region 16 over insulator 14, a doped region 18, a doped region 20, a gate dielectric 22, and a gate 24. Doped regions 18 and 20 are doped to N− by an implant using gate 24 as a mask. This implant is chosen to be of a sufficiently low power so the resulting doped region does not reach all the way to the insulator 14. The gate can be of an appropriate material. Most commonly, gates are made from polysilicon. Similarly, gate dielectric 22 may be of any suitable material. Most commonly, gate dielectrics are thermally grown oxide. Body 16 is a semiconductor material and is most commonly now silicon. The dopant for N-type is typically phosphorus or arsenic.

#Shown in FIG. 2 is device structure 10 after a mask 26 has been formed over a portion of gate 24 and doped region 18 and after an angled implant of P-type material has been performed. Photoresist is the preferred mask but other masks that can form this function would acceptable. The angled implant, about 25 degrees from vertical, is similar to the halo implant that is commonly performed for transistors to reduce problems with punchthrough. In this case the resulting doped region 27 reaches to the surface of body 16 as shown in a region underlapping gate 24 and is also below doped region 20. This is achieved by using a lower energy than would be used if a halo implant were being used simply to reduce punchthrough. Also this implant changes doped region 20 from N-type to P-type with a net doping less than that of region 27.