High-speed output buffer

A method for improving high-speed output buffer components comprising the steps of:

• establishing a cascode transistor module comprising two transistors, each of which has a control input and first and second current terminals;
• establishing a differential pair module comprising two transistors, each of which has a control input and first and second current terminals;
• said cascode module connected to receive at its second current terminals a substantially differential current signal from the first terminals of said differential pair module and to transmit at its first current terminals said substantially differential current signal into a pair of external load impedances as a first output waveform and a second output waveform;
• engineering the resistive loads seen by the first terminals of said differential pair module, based on one or more criteria thereby engineering the symmetry between the rising edge and the falling edge for each of said first output waveform and said second output waveform;
• and
• preconditioning the signal input applied to said differential pair module's control inputs.

A method for improving high-speed output buffer components comprising the steps of:

• establishing a cascode transistor module comprising two transistors, each of which has a control input and first and second current terminals;
• establishing a differential pair module comprising two transistors, each of which has a control input and first and second current terminals;
• said cascode module connected to receive at its second current terminals a substantially differential current signal from the first terminals of said differential pair module and to transmit at its first current terminals said substantially differential current signal into a pair of external load impedances as a first output waveform and a second output waveform;
• engineering the resistive loads seen by the first terminals of said differential pair module, based on one or more criteria thereby engineering the symmetry between the rising edge and the falling edge for each of said first output waveform and said second output waveform;
• and
• establishing a driving stage which provides a signal input to the control inputs of the transistors of said differential pair module, and engineering the output resistance of said driving stage.

A method for improving high-speed output buffer components comprising the steps of:

• establishing a cascode transistor module comprising two transistors, each of which has a control input and first and second current terminals;
• establishing a differential pair module comprising two transistors, each of which has a control input and first and second current terminals;
• said cascode module connected to receive at its second current terminals a substantially differential current, signal from the first terminals of said differential pair module and to transmit at its first current terminals said substantially differential current signal into a pair of external load impedances as a first output waveform and a second output waveform;
• and
• engineering the resistive loads seen by the first terminals of said differential pair module, based on one or more criteria thereby engineering the symmetry between the rising edge and the falling edge for each of said first output waveform and said second output waveform;
• wherein said pair of external load impedances comprise one or more inductive modules.

An improved high-speed output buffer component comprising:

• a cascode transistor module comprising two transistors, each of which has a control input and first and second current terminals;
• a differential pair module comprising two transistors, each of which has a control input and first and second current terminals, said cascode transistor module arranged to receive at its second current terminals substantially differential current signal from the first terminals of said differential pair module and to transmit at its first current terminals said substantially differential current signal into a pair of external load impedances as a first output waveform and a second output waveform, wherein said cascode transistor module further comprises:
• a resistive load comprising first and second resistances, said first resistance connected between the first terminal of one of said differential pair module transistors and the second terminal of one of said cascode module transistors, and said second resistance connected between the first terminal of the other of said differential pair module transistors and the second terminal of the other of said cascode module transistors;
• and
• a cascode bias voltage node for applying a cascode bias voltage to the control inputs of said cascode transistor module transistors, wherein the symmetry between the rising edge and the falling edge for each of said first output waveform and said second-output waveform may be altered by careful selection of one or more elements selected from the list of:
• said resistive load, and
• said cascode bias voltage.

An improved high-speed output buffer component comprising:

• a cascode transistor module comprising two transistors, each of which has a control input and first and second current terminals;
• a differential pair module comprising two transistors, each of which has a control input and first and second current terminals, said cascode transistor module arranged to receive at its second current terminals a substantially differential current signal from the first terminals of said differential pair module and to transmit at its first current terminals said substantially differential current signal into a pair of external load impedances as a first output waveform and a second output waveform, wherein said cascode transistor module further comprises:
• a resistive load comprising first and second resistances, said first resistance connected between the first terminal of one of said differential pair module transistors and the second terminal of one of said cascode module transistors, and said second resistance connected between the first terminal of the other of said differential pair module transistors and the second terminal of the other of said cascode module transistors;
• and
• a cascode bias voltage node for applying a cascode bias voltage to the control inputs of said cascode transistor module transistors, wherein the symmetry between the rising edge and the falling edge for each of said first output waveform and said second output waveform may be altered by careful selection of one or more elements selected from the list of:
• said resistive load, and
• said cascode bias voltage;
• and
• one or more stages for preconditioning a differential input signal applied to said differential pair module's control inputs.