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US 6,858,906 B2Granted
Floating trap non-volatile semiconductor memory devices including high dielectric constant blocking insulating layers
AssigneeSamsung Electronics Co., Ltd.
InventorsChang-Hyun Lee, Jung-Dal Choi, Byoung-Woo Ye
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Abstract
Floating trap non-volatile memory devices and methods are provided. The memory devices include a semiconductor substrate and an adjacent gate electrode. Between the substrate and the gate electrode may be a tunneling insulating layer having a first dielectric constant, a blocking insulating layer having a second dielectric constant that is greater than the first dielectric constant, and a charge storage layer.
Claims30
A floating trap non-volatile memory device comprising:
- a semiconductor substrate;
- a tunneling insulating layer having a first dielectric constant on the substrate;
- a charge storage layer on the tunneling insulating layer;
- a blocking insulating layer on the charge storage layer, the blocking insulating layer having a second dielectric constant which is greater than the first dielectric constant of the tunneling insulting layer;
- and
- a gate electrode on the blocking insulating layer.
3 more elements
A floating trap non-volatile memory device comprising:
- a semiconductor substrate;
- a plurality of parallel active regions on the semiconductor substrate;
- a plurality of parallel memory gate electrodes that intersect and pass over the active regions;
- a tunneling insulating layer having a first dielectric constant;
- a blocking insulating layer having a second dielectric constant that is greater than the first dielectric constant of the tunneling insulating layer;
- and
- a charge storage layer, wherein the tunneling insulating layer, the charge storage layer, and the blocking insulating layer are between the intersections of the active regions and the memory gate electrodes.
4 more elements
A floating trap non-volatile memory device comprising:
- a semiconductor substrate;
- a tunneling insulating layer having a first dielectric constant on the substrate;
- a charge storage layer on the tunneling insulating layer, the charge storage layer having a plurality of trap energy levels;
- a blocking insulating layer on the charge storage layer, the blocking insulating layer having a second dielectric constant which is greater than the first dielectric constant of the tunneling insulting layer;
- and
- a gate electrode on the blocking insulating layer.
3 more elements
Dependencies are inferred from the claim text.