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US 6,858,891 B2Granted
Nanotube semiconductor devices and methods for making the same
AssigneeMicron Technology, Inc.
InventorsWarren M. Farnworth, Kevin G. Duesman
Life of this patent
Estimating the term…
Abstract
Provided herein are vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices comprises a vertical transistor/capacitor cell including a nanotube. The device includes a vertical transistor and a capacitor cell both using a single nanotube to form the individual devices.
Claims24
A DRAM cell comprising:
- a vertical transistor including a gate, source, drain, and channel wherein a nanotube forms the channel;
- and
- a capacitor having a ground plate, an insulator, and a charge plate wherein the nanotube forms the charge plate.
A vertical transistor in a memory cell device, the vertical transistor comprising:
- a substrate;
- at least one nanotube connected substantially orthogonal to the substrate;
- a source and drain formed on the substrate;
- a conductive ring formed about an insulated exterior section of the nanotube, the conductive ring forming the gate of the vertical transistor;
- and
- wherein the nanotube forms a channel of the vertical transistor.
3 more elements
A memory cell capacitor comprising:
- a substrate having a first surface defining a plane;
- at least one nanotube connected substantially vertically to the substrate in relation to the plane;
- a ground cell plate formed on an exterior wall of the nanotube;
- and
- wherein the nanotube forms a cell of the capacitor.
2 more elements
A semiconductor device comprising:
- a substrate having a first surface;
- an insulator formed on the first surface of the substrate;
- a nanotube connected substantially perpendicular to the substrate;
- alternating layers of insulative material, and conductive material formed about an exterior wall of the nanotube, wherein the conductive layers form gates for multiple transistors;
- and
- wherein the nanotube forms an interconnection between the gates of the multiple transistors.
3 more elements
A semiconductor device having an electrical interconnect comprising:
- a substrate having a first surface defining a plane;
- a first trace formed on a portion of the substrate;
- a nanotube having a first end connected to the first trace, the nanotube being substantially vertical in relation to the plane defined by the first surface of the substrate;
- a second trace connected to a second end of the nanotube;
- and
- wherein the nanotube forms an electrical connection between the first trace and the second trace.
3 more elements
A semiconductor device comprising:
- a substrate;
- a first insulation layer formed on the substrate;
- at least one nanotube connected substantially orthogonal to the first insulation layer;
- a first conductive ring encircling a first end of the nanotube, the first conductive ring providing electrical connection from the nanotube to the substrate;
- a second insulation layer formed on the first conductive ring;
- a second conductive ring formed about an insulated exterior section of the nanotube, the second conductive ring electrically connected to the substrate;
- a third insulation layer formed on the second conductive ring;
- a third conductive ring encircling a second end of the nanotube, the third conductive ring providing electrical connection of the second end of the nanotube to the substrate;
- and
- a fourth insulation layer formed over the third conductive ring.
7 more elements
A semiconductor device comprising:
- a substrate;
- a first insulation layer formed on the substrate;
- at least one nanotube connected substantially orthogonal to the first insulation layer;
- a first conductive ring encircling and physically contacting an exterior wall of a first end of the nanotube, the first conductive ring providing electrical connection from the nanotube to the substrate;
- a second insulation layer formed on the first conductive ring;
- a second conductive ring encircling a first insulated exterior section of the nanotube, the second conductive ring electrically connected at a first end to the substrate;
- a third insulation layer formed on the second conductive ring;
- a third conductive ring encircling and physically contacting a second insulated exterior section of the nanotube, the third conductive ring electrically connected at a first end to the substrate;
- a fourth insulation layer formed on the third conductive ring;
- a fourth conductive ring encircling and physically contacting an exterior wall of a second end of the nanotube, the fourth conductive ring providing electrical connection of the second end of the nanotube to the substrate;
- and
- a fifth insulation layer formed on the fourth conductive ring.
9 more elements
A semiconductor device comprising:
- a substrate;
- a first insulation layer formed on the substrate;
- at least one nanotube connected substantially orthogonal to the first insulation layer;
- a first conductive ring encircling and physically contacting an exterior wall of a first end of the nanotube, the first conductive ring providing electrical connection from the nanotube to the substrate;
- a second insulation layer formed on the first conductive ring;
- a second conductive ring encircling and physically contacting an insulated exterior section of the nanotube, the second conductive ring electrically connected at a first end to the substrate;
- a third insulation layer formed on the second conductive layer;
- and
- a conductive layer on the third insulation layer, the conductive layer forming a capacitor ground cell plate, the ground cell plate electrically connected to the substrate.
6 more elements
A memory cell comprising:
- a vertical transistor including a gate, source, drain, and channel wherein a nanotube forms the channel;
- and
- a capacitor.
A semiconductor memory device comprising:
- a substrate having electrical circuitry formed thereon;
- a plurality of nanotubes connected substantially orthogonal to the substrate;
- a conductive ring about the exterior of the nanotubes, the conductive ring providing electrical connection from the nanotubes to the electrical circuitry on the substrate;
- and
- wherein the nanotubes form a cell of a capacitor and a channel of a transistor.
2 more elements
Dependencies are inferred from the claim text.