Optimization of abutted-pin hierarchical physical design
AssigneeReshape, Inc.
InventorsPeter Dahl, Byron Dickinson, Margie Levine, Paul Rodman
Life of this patent
Estimating the term…
Abstract
An abutted-pin hierarchical physical design process is described. The abutted-pin hierarchical physical design provides solutions to the problems of the traditional hierarchical physical design and provides additional advantages and benefits. In particular, the abutted-pin hierarchical physical design does not have channels. Moreover, in the abutted-pin hierarchical physical design, components of the top-level are merged into the block-level so that the top-level netlist is reduced significantly.
Claims52
A method of improving a physical design of a current integrated circuit, comprising the steps of:
- a) receiving a netlist of said current integrated circuit;
- b) receiving physical design information from a prior integrated circuit;
- and
- c) generating said physical design based on said netlist and said physical design information.
A computer-readable medium comprising computer-executable instructions stored therein for performing a method of improving a physical design of a current integrated circuit, said method comprising:
- a) receiving a netlist of said current integrated circuit;
- b) receiving physical design information from a prior integrated circuit;
- and;
- c) generating said physical design based on said netlist and said physical design information.
A method of determining a plurality of pins for each block of a physical design of a current integrated circuit, comprising:
- a) receiving a netlist of said current integrated circuit;
- b) receiving physical design information from a prior integrated circuit, wherein said physical design information includes pin assignments of blocks of said prior integrated circuit;
- c) using said netlist and said physical design information to perform a top-level placement for a plurality of ports corresponding to each block of said current integrated circuit;
- d) using said netlist and said physical design information to perform a top-level route for said ports to determine pin assignments for each block of said current integrated circuit;
- and
- e) generating each pin for each block based on said top-level route to determine pin assignments.
A computer-readable medium comprising computer-executable instructions stored therein for performing a method of determining a plurality of pins for each block of a physical design of a current integrated circuit, comprising:
- a) receiving a netlist of said current integrated circuit;
- b) receiving physical design information from a prior integrated circuit, wherein said physical design information includes pin assignments of blocks of said prior integrated circuit;
- c) using said netlist and said physical design information to perform a top-level placement for a plurality of ports corresponding to each block of said current integrated circuit;
- d) using said netlist and said physical design information to perform a top-level route for said ports to determine pin assignments for each block of said current integrated circuit;
- and
- e) generating each pin for each block based on said top-level route to determine pin assignments.
Dependencies are inferred from the claim text.