US 6,857,113 B2 · Process and system for identifying wires at risk of electromigration

Abstract

A method and system of identifying one or more nets in a digital IC design that are at risk of electromigration comprises selecting a manufacturing process for the digital IC design and obtaining a clock period and process voltage. A voltage waveform transition time and effective capacitance is calculated for one or more of the nets. A maximum allowable effective capacitance for each one of the nets is calculated based upon a peak current analysis or an RMS current analysis. The effective capacitance for each net is compared against the maximum allowable capacitance to identify those nets that are at risk of failure due to the effects of electromigration.

Claims26

Dependent claims

A method of identifying one or more nets in a digital IC design that are at risk of electromigration comprising the steps of:

selecting a manufacturing process for said digital IC design,
obtaining a clock period and process voltage for said digital IC design,
obtaining a voltage waveform transition time for one or more nets of said digital IC design,
calculating a maximum effective capacitance for each one of said one or more nets as a function of a maximum allowable current density through a wire that comprises said net, a maximum allowable current density through a via that comprises said net, a minimum width of said wire, and minimum number of parallel vias per net,
calculating an effective capacitance for each one of said one or more nets, and
comparing said maximum allowable effective capacitance against each said effective capacitance.

3 more elements

A system for identifying one or more nets in a digital IC design that are at risk of electromigration comprising:

a processing element having memory and operatively communicating with a display device, and having an operating system for performing commands dictated by a program, said program comprising:
means for obtaining a clock period and process voltage for said digital IC design,
means for obtaining a voltage waveform transition time for one or more nets of said digital IC design,
means for calculating a maximum effective capacitance for each one of said one or more nets as a function of a maximum allowable current density through a wire that comprises said net, a maximum allowable current density through a via that comprises said net, a minimum width of said wire, and minimum number of parallel vias per net,
means for calculating an effective capacitance for each one of said one or more nets and
means for comparing said maximum allowable effective capacitance against each said effective capacitance.

3 more elements

Dependencies are inferred from the claim text.

Process and system for identifying wires at risk of electromigration

Life of this patent

Process and system for identifying wires at risk of electromigration

Life of this patent

Abstract

Claims26