LSI layout method and apparatus for cell arrangement in which timing is prioritized

An LSI layout system for performing layout of an LSI having a plurality of cells, comprising:

• automated arrangement unit for performing automated arrangement of cells on a chip on the basis of a netlist, which has a plurality of cells and connection data therefor, and cell timing conditions data;
• global wiring processing unit for generating wiring connecting said cells with alleviating conditions for short circuits between wiring;
• timing optimization processing unit for optimizing a timing of the cells in accordance with the signal propagation time of the wiring connecting said automatically arranged cells;
• congestion rate analysis processing unit for seeking a congestion rate of said wiring, and detecting regions for which the congestion rate is higher than a reference level;
• cell rearrangement processing unit for performing rearrangement processing of said cells in small associated regions for which the congestion rate is higher than the reference level, said chip being divided into a plurality of small associated regions;
• and
• detailed wiring processing unit for generating wiring connecting the cells, after said cell rearrangement processing, such that short circuits between wiring are forbidden,
• wherein, after said cell rearrangement processing by the cell rearrangement processing unit in the small associated region for which the congestion rate is higher than the reference level, wiring congestion rate analysis is performed once again by the congestion rate analysis processing unit, and
• in a case wherein the congestion rate does not exceed the reference level, detailed wiring processing is performed by the detailed wiring processing unit;
• and
• wherein, in a case in which there is a region for which the congestion rate exceeds the reference level, a size of said small associated region is increased to perform the cell rearrangement processing once again by the cell rearrangement processing unit.

An LSI layout program for making a computer perform layout of an LSI having a plurality of cells, comprising:

• an automated cell arrangement program for performing automated arrangement of cells on a chip on the basis of a netlist, which has a plurality of cells and connection data therefor, and cell timing conditions data;
• a global wiring processing program for generating wiring connecting said cells with alleviating conditions for short circuits between wiring;
• a timing optimization processing program for optimizing timing of the cells in accordance with the signal propagation time of the wiring connecting said automatically arranged cells;
• a congestion rate analysis processing program for seeking a congestion rate of said wiring, and detecting regions for which the congestion rate is higher than a reference level;
• a cell rearrangement processing program for performing rearrangement processing of said cells in small associated region for which the congestion rate is higher than the reference level, said chip being divided into a plurality of small associated regions;
• and
• a detailed wiring processing program, for generating wiring connecting the cells, after said cell rearrangement processing, such that short circuits between wiring are denied,
• wherein, after said cell rearrangement processing in the small associated region for which the congestion rate is higher than the reference level, wiring congestion rate analysis is performed once again, and
• in a case wherein the congestion rate does not exceed the reference level, said detailed wiring processing is performed;
• and
• wherein, in a case in which there is a region for which the congestion rate exceeds the reference level, a size of said small associated is increased to perform the cell rearrangement processing once again.

A wiring congestion minimizing layout method for an LSI having a plurality of cells, wherein a plurality of cells are automatically arranged on a chip on the basis of a netlist having connection data and cell timing conditions data, the cells are divided into a plurality of regions of a predetermined size, and wiring is generated connecting said cells to alleviate conditions for short circuits between wiring and to optimize signal propagation time of the wiring connecting said automatically arranged cells, the method comprising:

• determining a congestion rate of the wiring in each of the plurality of regions and for each region:
• where the congestion rate for a region is less than or equal to the reference level:
• performing detailed wiring processing to eliminate short circuits between wiring;
• and
• where the congestion rate for the region is greater than the reference level:
• rearranging the cells in the region for which the congestion rate is greater than the reference level;
• determining whether the congestion rate of the region having the rearranged cells is greater than the reference level and, where the congestion rate for the region is greater than the reference level, repeating the following operations until the congestion rate for the region is less than or equal to the reference level:
• enlarging the region to a next predetermined size;
• rearranging the cells in the enlarged region;
• and
• determining whether the congestion rate of the rearranged cells in
• the enlarged region is greater than the reference level;
• and
• upon determining that the congestion rate for the region is less than or equal to the reference level, performing detailed wiring processing to eliminate short circuits between wiring.