Method and apparatus to facilitate self-testing of a system on a chip

A method of testing a system-on-a-chip including a processor and a configurable system logic (CSL), the method comprising:

• performing a plurality of tests on the CSL using vector arrays to write data, to verify that banks and interconnections between the banks are functioning;
• generating a single cyclic redundancy check (CRC) output of the tests;
• and
• if the CRC result corresponds to an expected result, passing the system-on-a-chip.

A method of testing a system-on-a-chip including a processor and a configurable system logic, the method comprising:

• testing configuration memory by writing to each memory location, and performing a cyclic redundancy check (CRC) on a result;
• testing multiplexers (MUXes) by:
• isolating a plurality of the MUXes;
• driving signals to an un-isolated MUX;
• and
• reading an output of the MUX to verify a test result.

A system-on-a-chip including self-test capabilities, the system-on-a-chip comprising:

• a processor;
• a configurable system logic (CSL) including a plurality of banks arranged in an array coupled to the processor;
• and
• a built-in self test (BIST) mechanism coupled to the CSL to perform tests on the CSL to verify that the banks and interconnections between the banks are functioning properly, the BIST mechanism including:
• a master copy of data to be written to a plurality of locations;
• and
• a reproduction mechanism to write slave copies across the entire CSL from the master copy, using vectors to perform a broadcast write.