Hierarchy of fault isolation timers
AssigneeHewlett-Packard Development Company, L.P.
InventorMark Shaw
Life of this patent
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Abstract
In the present invention, a coordinated hierarchy of timing mechanisms preferably cooperate to report errors at different operational levels of a complex of computing devices. Preferably, each timer is able to identify a failure condition at its own level of operation and transmit a time-out condition to a higher level device which may also be a timer. Upon generation of a time-out condition, a system component experiencing a fault condition preferably continues to operate in a degraded mode, informs devices attempting to communicate with the faulty component of a status of the fault condition, and preferably proceeds to identify and correct a failure which caused the time out condition. The timers may be implemented in hardware or software.
Claims20
A method for isolating a fault condition in a complex of computing devices comprising a plurality of CPUs, a plurality of I/Os and a plurality of CPU interface controllers, the method comprising:
- monitoring a plurality of transactions being executed within said complex with a plurality of timers;
- establishing a hierarchy of timers;
- setting an expiration time for each timer to progressively higher values at progressively higher levels of said hierarchy of timers;
- and
- upon expiration of a timer, transmitting a time-out condition to a next higher level timer in said hierarchy of timers, thereby indicating a fault condition within a component of said complex including said expired timer, wherein said component is a faulty component.
A system for preserving an operation of a distributed computing complex during a fault condition that occurs during execution of a sequence of transactions, wherein the computing complex comprises a plurality of functional units, with each function unit comprising a plurality of CPUs, a plurality of I/O, and a plurality of CPU interface controllers, the system comprising:
- a plurality of timers for timing said sequence of transactions;
- means for setting expiration values of said plurality of timers to progressively lower levels for timers of said plurality of timers timing transactions in increasing proximity to a last transaction of the plurality of transactions to form a hierarchy of timers;
- means for transmitting a time-out condition to a next higher level timer of said plurality of timers upon expiration of a timer of said plurality of timers;
- means for logging an error at said higher level timer, thereby identifying a fault condition within a faulty functional unit in said complex;
- means for informing the other functional components of said complex of said fault condition in said faulty functional component of said complex, thereby avoiding propagation of said fault condition to said other functional components of said complex and preserving the operation of said complex during said fault condition.
A computer program product having a computer readable medium having computer program logic recorded thereon for isolating a fault condition in a complex of computing devices executing a sequence of transactions, the computer program product comprising:
- code for establishing a hierarchy of timers;
- code for setting an expiration time for each timer to progressively higher values at progressively higher levels of said hierarchy of timers;
- and
- code for transmitting a time-out condition to a next higher level timer in said hierarchy of timers upon expiration of a timer, thereby indicating a fault condition within a component of said complex including said expired timer, wherein said component is a faulty component.
Dependencies are inferred from the claim text.