Multiprocessor system and method for simultaneously placing all processors into debug mode
AssigneeLSI Logic Corporation
InventorChristopher M. Giles
Life of this patent
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Abstract
Multiple processors of a multiprocessor system are placed into a debug mode of operation approximately simultaneously when one processor initially enters the debug mode as a result of incurring a debug event. The other processors enter the debug mode as a result of the one processor asserting a debug event signal upon initially entering the debug mode. A logic circuit associated with each processor responds to any debug event signal asserted by another processor and the failure of its associated processor to assert a debug event signal, to assert an external debug break signal to the associated processor and place the associated processor into the debug mode.
Claims25
In a system having multiple processors wherein each processor enters a debug mode of operation as a result of incurring a debug event, an improvement comprising:
- a debug interface associated with each one processor which asserts a debug event signal when the associated one processor enters the debug mode as a result of incurring an internal debug event;
- and
- a logic circuit associated with each processor and receptive of the debug event signal supplied by each other processor of the system, each logic circuit responding to the debug event signal supplied by each other processor to assert an external debug break signal to the processor associated with the logic circuit;
- and
- the debug interface further responds to the external debug break signal supplied by the associated logic circuit to place the processor into the debug mode.
A method of approximately simultaneously halting execution of instructions by each processor of a system having multiple processors upon one of the processors of the system entering a debug mode of operation as a result of incurring a debug event, comprising:
- halting execution of instructions by the one processor to place that one processor into a debug mode of operation upon that one processor incurring a debug event;
- and
- after halting execution of instructions by the one processor, placing each other processor of the system into a debug mode of operation approximately simultaneously with the one processor entering the debug mode of operation by sending an external debug break signal from the one processor to each other processor of the system to cause each other processor to enter the debug mode of operation.
Dependencies are inferred from the claim text.