Method and system for triggering a debugging unit

A microprocessor, comprising:

• a debugging unit operable to transition from a first operating state to a second operating state in response to a first signal;
• a processor core operable to fetch an instruction stream including a second signal representative of a first triggering instruction to transition said debugging unit from said first operating state to said second operating state, said processor core further operable to provide said first signal to said debugging unit in response to said second signal, said debugging unit is further operable to transition from said second debugging operating state to a third debugging operating state in response to a third signal;
• said instruction stream further includes a fourth signal representative of a second triggering instruction to transition said debugging unit from said second debugging operating state to said third debugging operating state;
• and
• said processor core is further operable to provide said third signal to said debugging unit in response to said fourth signal.

A computer readable medium storing computer readable code which is executable for transitioning a debugging unit between a plurality of operating states, comprising:

• a first computer readable code to operate a processor core;
• a second computer readable code to transition the debugging unit from a first operating state to a second operating state, said second computer readable code embedded within said first computer readable code;
• and
• a third computer readable code to transition the debugging unit from said second operating state to a third operating state, said third computer readable code embedded within said first computer readable code.

A system for transitioning a debugging unit between a plurality of operating states, comprising:

• a computer readable medium including a first computer readable code to transition the debugging unit from a first operating state to a second operating state, said computer readable medium operable to provide a first signal representative of said first computer readable code;
• a processor core operable to provide a second signal to the debugging unit in response to said first signal whereby the debugging unit is operable to transition from the first operating state to the second operating state wherein said processor core includes a register operable provide said second signal in response to a third signal including an address of said register;
• and
• said computer readable medium further includes a second computer readable code to transition the debugging unit from the second operating state to a third operating state, said computer readable medium operable to provide a third signal representative of said second computer readable code;
• and
• said processor core is further operable to provide a fourth signal to the debugging unit in response to said third signal whereby the debugging unit is operable to transition from the second operating state to the third operating state.

A method for transitioning a debugging unit between a plurality of operating states, comprising:

• receiving a first signal representative of a first triggering instruction to transition the debugging unit from a first operating state to a second operating state;
• processing said first signal to thereby transition the debugging unit from said first operating state to said second operating state;
• and
• receiving a second signal representative of a second triggering instruction to transition the debugging unit from said second operating state to a third operating state;
• and
• processing said second signal to thereby transition the debugging unit from said second operating state to said third operating state.

A method for transitioning a debugging unit between a plurality of operating states, comprising:

• receiving a set of operating signals representative of a set of operating instructions to generate a first data or a second data;
• receiving a trigger instruction signal representative of a triggering instruction to transition the debugging unit from a first operating state to a second operating state in response to a generation of said first data and to transition the debugging unit from said first operating state to a third operating state in response to a generation of said second data;
• and
• processing said set of operating signals and said trigger instruction signal to thereby transition the debugging unit from said first operating state to said second operating state in response to a generation of said first data and to thereby transition the debugging unit from said first operating state to said third operating state in response to a generation of said second data.

A method, comprising:

• providing a computer readable medium operable to provide a set of operating signals representative of a set of operating instructions to generate a first data or a second data, and a trigger instruction signal representative of a triggering instruction to transition said debugging unit from a first operating state to a second operating state or to transition said debugging unit from said first operating state to a third operating state;
• providing a processor core operable to generate said first data or said trigger data in response to said set of operating signal, to provide a first triggering signal subsequent to a generation of said first data in response to said triggering instruction signal, and to provide a second triggering signal subsequent to a generation of said second data in response to said triggering instruction signal;
• and
• providing a debugging unit operable to transition from said first operating state to said second operating state in response to said first triggering signal and to transition from said first operating state to said third operating state in response to said second triggering signal.