Multi-link receiver mechanism for processing multiple data streams

A multi-link receiving mechanism comprising:

• a first receiver coupled to receive a first data stream and a clock signal, said first data stream comprising a first plurality of data units, said first receiver delaying said clock signal by a first variable delay to derive a first reference signal, and generating a first plurality of latching control signals based upon said first reference signal to latch said first plurality of data units;
• and
• a second receiver coupled to receive a second data stream and said clock signal, said second data stream comprising a second plurality of data units, said second receiver delaying said clock signal by a second variable delay to derive a second reference signal, and generating a second plurality of latching control signals based upon said second reference signal to latch said second plurality of data units;
• wherein said first data stream and said second data stream are not aligned with each other when received by said first receiver and second receiver, respectively;
• wherein said clock signal is not necessarily aligned with either said first data stream or said second data stream;
• wherein said first variable delay and said second variable delay are different delays;
• and
• wherein each of said first plurality of data units occupies one data period;
• wherein each of said second plurality of data units occupies one data period;
• and
• wherein both said first variable delay and said second variable delay are greater than or equal to one data period.

A multi-link receiving mechanism comprising:

• a first receiver coupled to receive a first data stream and a clock signal, said first data stream comprising a first plurality of data units, said first receiver delaying said clock signal by a first variable delay to derive a first reference signal, and generating a first plurality of latching control signals based upon said first reference signal to latch said first plurality of data units;
• and
• a second receiver coupled to receive a second data stream and said clock signal, said second data stream comprising a second plurality of data units, said second receiver delaying said clock signal by a second variable delay to derive a second reference signal, and generating a second plurality of latching control signals based upon said second reference signal to latch said second plurality of data units;
• wherein said first data stream and said second data stream are not aligned with each other when received by said first receiver and second receiver, respectively,
• wherein said clock signal is not necessarily aligned with either said first data stream or said second data stream;
• wherein each of said first plurality of data units occupies one data period, and wherein said first receiver generates no more than one of said first plurality of latching control signals per data period;
• wherein each of said first plurality of latching control signals coincides approximately with a midpoint of a data period corresponding to one of said first plurality of data units;
• wherein each of said second plurality data units occupies one data period, and
• wherein said second receiver generates no more than one of said second plurality of latching control signals per data period;
• wherein each of said second plurality of latching control signals coincides approximately with a midpoint of a data period corresponding to one of said second plurality of data units;
• wherein said first receiver comprises a first delay control mechanism for adjusting said first variable delay, and wherein said second receiver comprises a second delay control mechanism for adjusting said second variable delay;
• wherein said first delay control mechanism adjusts said first variable delay to cause said first receiver to generate said first plurality of latching control signals such that each of said first plurality of latching control signals coincides more closely with a midpoint of a data period corresponding to one of said first plurality of data units;
• wherein said second delay control mechanism adjusts said second variable delay to cause said second receiver to generate said second plurality of latching control signals such that each of said second plurality of latching control signals coincides more closely with a midpoint of a data period corresponding to one of said second plurality of data units;
• wherein said first delay control mechanism includes a detection mechanism to receive an indication of how closely each of said first plurality of latching control signals coincides with a midpoint of a data period corresponding to one of said first plurality of data units and to provide an adjustment signal to adjust said first variable delay;
• wherein said detection mechanism comprises a phase detector, wherein said first delay control mechanism further comprises:
• a fixed delay element coupled to receive at least one of said first plurality of latching control signals and providing a delayed latching signal;
• and
• a latching component coupled to receive said first data stream, said latching component latching one of said first plurality of data units in response to said delayed latching signal;
• and
• wherein said detection mechanism receives said one of said first plurality of data units, and compares said one data unit with a plurality of other data units from said first plurality of data units to determine how closely each of said first plurality of latching control signals coincides with a midpoint of a data period corresponding to one of said first plurality of data units.