US 6,857,063 B2 · Data processor and method of operation

Abstract

A data processor executes an instruction (JAVASW) to implement efficient interpreter functionality by combining the tasks of table jumps and thread or task switching which is controlled by a running value such as a counter or a timer. Execution of the instruction always requires a change of flow to be taken. In one form, the instruction may cause a hardware accelerator to be signaled to complete instruction execution. Additionally, a memory table containing emulation code correlated to specific byte codes may be compressed for a large number of identified byte codes by the use of separate storage. Further, use of a same portion of the memory table may occur in connection with execution of different bytecodes. While discussed in the context of Java bytecodes, the instruction is applicable to any programming language and processor architecture.

Claims23

Dependent claims

A method of program execution in a data processing system comprising:

means for fetching a first instruction located at a first address;
and
means for executing the first instruction with the data processing system, the method comprising:
executing the first instruction;
selecting a jump address based upon a value by providing a second address for the jump address if a comparison of the value with a predetermined value has a first result, and providing a third address for the jump address if the comparison of the value with the predetermined value has a second result, wherein neither the second address nor the third address is contiguous to the first address;
and
always implementing a change of control in the program execution in response to executing the first instruction by redirecting program execution to the jump address.

4 more elements

A data processing system comprising:

a memory for storing a plurality of program instructions:
an instruction register coupled to the memory via a data bus for receiving the program instructions;
an instruction decoder coupled to the instruction register for decoding the program instructions into specific opcode values;
a control circuit coupled to the instruction decoder for providing control signals in response to the specific opcode values, the control circuit using a user determinable control signal that selects instruction group size;
address generation circuitry coupled to the control circuit for receiving the control signals and creating the jump address;
registers coupled to the address generation circuitry for storing operands in response to the control circuit;
an arithmetic logic unit coupled to the address generation circuitry and the control circuit, the arithmetic logic unit processing the operands stored by the registers;
a storage device for storing a plurality of processing instructions to be executed by the arithmetic logic unit, the plurality of processing instructions arranged in groups wherein each group is correlated to a predetermined one of the plurality of program instructions;
and
the arithmetic logic unit executing a predetermined processing instruction at a predetermined address and selecting a jump address based upon a value by providing a first address for the jump address if a comparison of the value with a predetermined value has a first result, and by providing a second address for the jump address if the comparison of the value with the predetermined value has a second result, wherein neither the first address nor the second address is contiguous to the predetermined address, execution of the predetermined processing instruction always implementing a change if control in program execution.

7 more elements

Dependencies are inferred from the claim text.

Data processor and method of operation

Life of this patent

Data processor and method of operation

Life of this patent

Abstract

Claims23