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US 6,857,060 B2Granted
System, apparatus and method for prioritizing instructions and eliminating useless instructions
AssigneeIntel Corporation
InventorsGeorge Elias, Adi Yoaz, Ronny Ronen
Life of this patent
Estimating the term…
Abstract
According to one embodiment, a method features operations for executing instructions in an instruction window. The first and second instructions are examined to determine their sources and destinations. The written on bit of the first instruction is set to a “written on” state if the destinations of the first and second instructions are the same while a used bit of the first instruction is set to a “used” state if the source of the second instruction is the destination of the first instruction. Thereafter, a priority of the first instruction can be determined from the written on and used bits.
Claims25
A method, comprising:
- examining a first instruction to determine a first destination that the first instruction will write on, the first instruction to be in an instruction window;
- examining a second instruction to determine a first source that the second instruction will use and a second destination that the second instruction will write on, the second instruction to enter the instruction window;
- setting a written on bit associated with the first instruction to a written on state if the first destination and the second destination will be the same operand;
- setting a used bit associated with the first instruction to a used state if the first destination and the first source will be the same operand;
- determining a priority of the first instruction from the written on and used bits;
- and
- determining a number of times that at least one instruction to enter the instruction window after the first instruction will use the first destination as a source for the at least one instruction to enter the instruction window after the first instruction.
4 more elements
A method, comprising:
- examining a first instruction to determine a first destination that the first instruction will write on, the first instruction to be in an instruction window;
- examining a second instruction to determine a first source that the second instruction will use and a second destination that the second instruction will write on, the second instruction to enter the instruction window;
- setting a written on bit associated with the first instruction to a written on state if the first destination and the second destination will be the same operand;
- setting a used bit associated with the first instruction to a used state if the first destination and the first source will be the same operand;
- determining a priority of the first instruction from the written on and used bits;
- determining that the first instruction is useless if the first destination and the second destination are the same operand and if no instruction to enter the instruction window after the first instruction and before the second instruction will use the first destination as a source for the at least one instruction to enter the instruction window after the first instruction and before the second instruction;
- recording whether the instruction was useless, and
- predicting whether the instruction will be useless based on the recording whether the instruction was useless in past occurrences.
5 more elements
A method, comprising:
- examining a first instruction to determine a first destination that the first instruction will write on, the first instruction to be in an instruction window;
- examining a second instruction to determine a first source that the second instruction will use and a second destination that the second instruction will write on, the second instruction to enter the instruction window;
- setting a written on bit associated with the first instruction to a written on state if the first destination and the second destination will be the same operand;
- setting a used bit associated with the first instruction to a used state if the first destination and the first source will be the same operand;
- determining a priority of the first instruction from the written on and used bits;
- determining how many instructions will enter the instruction window after the first instruction and before the second instruction if the first destination and the first source are the same operand;
- and,
- refining the priority of the first instruction based on the how many instructions will enter the instruction window after the first instruction and before the second instruction if the first destination and the first source are the same operand.
5 more elements
A processor, comprising:
- an instruction window including a plurality of instruction entries including a first instruction entry and a second instruction entry, each instruction entry including an instruction field to be occupied by an instruction, a written on bit, a used bit, and a priority field determined from the written on bit and the used bit, the used bit of the first instruction entry has a default value to be based on the type of instruction occupying the instruction field;
- and
- a fetcher to store a prior instruction in the first instruction entry and to store a subsequent instruction in the second instruction entry, the prior instruction and the subsequent instruction include a source and a destination.
A processor, comprising:
- an instruction window including a plurality of instruction entries including a first instruction entry and a second instruction entry, each instruction entry including an instruction field to be occupied by an instruction, a written on bit, a used bit, and a priority field determined from the written on bit and the used bit, the used bit of the first instruction entry to be set to a used state if the source of the subsequent instruction and destination of the prior instruction are the same operand;
- and
- a fetcher to store a prior instruction in the first instruction entry and to store a subsequent instruction in the second instruction entry, the prior instruction and the subsequent instruction include a source and a destination, the fetcher to further store one or more instructions that intervene between the prior instruction and the subsequent instruction in one or more instruction entries of the plurality of instruction entries by including an intervening instruction field in each of the plurality of entries.
A processor, comprising:
- an instruction window including a plurality of instruction entries including a first instruction entry and a second instruction entry, each instruction entry including an instruction field to be occupied by an instruction, a written on bit, a used bit, and a priority field determined from the written on bit and the used bit;
- a fetcher to store a prior instruction in the first instruction entry and to store a subsequent instruction in the second instruction entry, the prior instruction and the subsequent instruction include a source and a destination;
- and
- a used count field of the first instruction entry to determine how many instruction entries other than the first instruction entry are occupied by instructions including a source that is the destination of the prior instruction.
1 more element
A processor, comprising:
- an instruction window including a plurality of instruction entries including a first instruction entry and a second instruction entry, each instruction entry including an instruction field to be occupied by an instruction, a written on bit, a used bit, and a priority field determined from the written on bit and the used bit;
- a fetcher to store a prior instruction in the first instruction entry and to store a subsequent instruction in the second instruction entry, the prior instruction and the subsequent instruction include a source and a destination;
- means for record a priority of at least one instruction;
- and
- means for predicting the priority of the at least one instruction based on the recorded priority.
2 more elements
A processor comprising:
- an instruction window having a plurality of instruction entries including a first instruction entry, a second instruction entry, and a third instruction entry of the plurality of instruction entries, each instruction entry including an instruction field to be occupied by an instruction, a written on bit, a used bit, and a priority field determined from the written on bit and the used bit and an intervening instruction field of the first instruction entry to determine how many of the plurality of instruction entries is occupied by an intervening instruction if the source of the subsequent instruction is the destination of the prior instruction and if no source of the intervening instructions is the destination of the prior instructions;
- a memory;
- a fetcher to fetch instructions from the memory and to store a prior instruction in the first instruction entry and to store a subsequent instruction in the second instruction entry, both the prior instruction and subsequent instruction include a source, a destination, the written on bit of the first instruction entry to be set to a written on state if the destination of the prior instruction and the subsequent instruction are the same operand, and the used bit of the first instruction entry to be set to a used state if the source of the subsequent instruction and the destination of the prior instruction are the same operands, the fetcher is further to store an instruction that intervenes between the prior instruction and the subsequent instruction in the third instruction entry;
- and,
- an intervening instruction field of the first instruction entry to determine how many of the plurality of instruction entries is occupied by an intervening instruction if the source of the subsequent instruction is the destination of the prior instruction and if no source of the intervening instructions is the destination of the prior instruction.
2 more elements
A circuit, comprising:
- a written on logic to determine a written on bit;
- a used logic to determine a used bit;
- and,
- a priority logic to determine a priority based on the written on and the used bits, the written on, used and priority logics to be associated with a first instruction entry of a plurality of instruction entries in an instruction window, the plurality of instruction entries to include a second instruction entry, the first instruction entry to be occupied by a prior instruction and the second instruction entry to be occupied by a subsequent instruction, the first and second instructions each include a source and a destination, the priority logic to set the priority to redundant if the written on bit is set to a written on state and the used bit is set to a not used state.
1 more element
A circuit comprising:
- a written on logic to determine a written on bit;
- a used logic to determine a used bit;
- and,
- a priority logic to determine a priority based on the written on and the used bits, the written on, used and priority logics to be associated with a first instruction entry of a plurality of instruction entries in an instruction window, the plurality of instruction entries to include a second instruction entry, the first instruction entry to be occupied by a prior instruction and the second instruction entry to be occupied by a subsequent instruction, the first and second instructions each include a source and a destination;
- and
- a used count logic to determine how many of the plurality of instruction entries are occupied by an instruction that is subsequent to the prior instruction and that has a source that is the same operand as the destination of the prior instruction.
3 more elements
A circuit comprising:
- a written on logic to determine a written on bit;
- a used logic to determine a used bit;
- and,
- a priority logic to determine a priority based on the written on and the used bits, the written on, used and priority logics to be associated with a first instruction entry of a plurality of instruction entries in an instruction window, the plurality of instruction entries to include a second instruction entry, the first instruction entry to be occupied by a prior instruction and the second instruction entry to be occupied by a subsequent instruction, the first and second instructions each include a source and a destination;
- and
- a predicting logic to predict the priority of the at least one instruction based on the recorded priority.
3 more elements
Dependencies are inferred from the claim text.