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US 6,857,058 B1Granted
Apparatus to map pages of disparate sizes and associated methods
AssigneeIntel Corporation
InventorsNagasubramanian Gurumoorthy, Shivaprasad Sadashivaiah
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AssigneeIntel Corporation
InventorsNagasubramanian Gurumoorthy, Shivaprasad Sadashivaiah
Estimating the term…
A data processing system providing high performance two-dimensional and three-dimensional graphics includes at least one system processor, chipset core logic, a graphics processor, main memory storing computer software and data including operating system software, and a graphics address remapping table (GART). The chipset logic operates on first-sized memory pages, while the operating system operates on larger, second-sized memory pages. In one embodiment GART driver software maps each second-sized page to Z first-sized pages by filling up the GART with Z entries per second-sized page, where Z is the rounded integer number of first-sized pages per second-sized page. In another embodiment, an address translation function converts a first page number, corresponding to a first-sized page, issuing from a system processor into a second page number, corresponding to a second-sized page, and a page offset within the second-sized page. Also described is an integrated circuit for mapping memory pages of disparate sizes, and a computer-readable medium storing a data structure for implementing the page mapping method and apparatus.
A method performed by a data processing system comprising a processor, a logic device, and a memory coupled to the processor and to the logic device, the logic device operating upon data organized in first-sized pages, and the memory storing an operating system in second-sized pages, the method comprising the following operations:
A data processing system comprising a processor, a logic device, and a memory coupled to the processor and to the logic device, the logic device to operate upon data organized in first-sized pages, and the memory organized in second-sized pages, the system to execute a computer program stored on a computer storage medium, the computer program comprising the following operations:
A computer-readable medium having computer-executable instructions that, when executed, result in operations being performed in a data processing system, the data processing system comprising a processor, a logic device, and a memory coupled to the processor and to the logic device, the logic device to operate upon data organized in first-sized pages, and the memory organized in second-sized pages, the operations comprising:
An integrated circuit for use in a data processing system comprising a processor and a memory coupled to the processor, the circuit comprising a component to map memory pages of disparate sizes, the component to determine a size X of a first-sized page, to determine a size Y of a second-sized page, wherein X and Y are positive integers, the component to determine Z=Y/X, wherein Z is not an integer and Z is rounded up to the nearest integer, the component to receive from the processor a first page number to a table in the memory, the first page number to correspond to a first-sized page, and the component to provide a second page number to point to a starting address of a second-sized page in the memory, and a page offset within the second-sized page, the page offset to range from zero to the size of the first-sized page times the quantity (Z-1).
Dependencies are inferred from the claim text.