Multi-processor system including a mode switching controller
AssigneeSemiconductor Technology Academic Research Center
InventorHideharu Amano
Life of this patent
Estimating the term…
Abstract
Any of the processors CPU1 to CPUn turns the miss hit detecting signal line 5 to a low level upon detecting occurrence of a miss hit. In response, the mode switching controller 2 is notified of the occurrence of a miss hit and switches each of the processors CPU1 to CPUn to the synchronous operation mode. Also, each command from each of the processors CPU1 to CPUn is appended with a tag. When each of the processors CPU1 to CPUn feeds the synchronization detecting signal line 6 with the tags which are identical as designated as a synchronous point, the operation of the processors can be switched to the non-synchronous operation mode by the mode switching controller 2.
Claims12
A multi-processor system having a plurality of processors connected to each other via a data bus, said system comprising:
- communication memory modules respectively connected between the processors and the data bus;
- local memory modules respectively dedicated to said processors;
- cache memories connected respectively between the processors and the dedicated local memory modules;
- and
- a mode switching controller for controlling a switching of an operation mode of said processors,
- wherein each of the processors has a non-synchronous operation mode for executing a workload in parallel with respect to the other processors and a synchronous operation mode for executing a synchronous operation, and when a miss hit of a cache memory is detected in the non-synchronous operation mode by at least one of the processors, the operation mode of all the processors is entirely switched from the non-synchronous operation mode to the synchronous operation mode.
Dependencies are inferred from the claim text.