Back to results
US 6,857,051 B2Granted
Method and apparatus for maintaining cache coherence in a computer system
AssigneeIntel Corporation
InventorsVinod Sharma, Edward T. Grochowski
Life of this patent
Estimating the term…
Abstract
The computer system includes a processor having an associated cache to store a data segment in a Read Only state. For one embodiment, a Read Only state may indicate that no other processor of the system has a clean, valid copy of the segment. Before the processor may write to the segment in a Read Only state, however, the processor may first request ownership of the segment. As an alternative to storing the segment in a Read Only state, the segment may be stored in a Modified, Exclusive, Shared, Invalid or any other state.
Claims20
A computer system comprising:
- a processor;
- and
- a processor cache to store a first segment in a first state of a cache coherence protocol, the first state being a Read-Only state in which no other processor of the computer system may have a clean, valid copy of the first segment, and in which the processor is to request ownership of the first segment before the processor may write to the segment.
A method comprising:
- enabling a first segment to be stored in a first state in a processor cache of a computer system, the first state being a Read-Only state in which no other processor of the computer system may have a clean, valid copy of the first segment;
- and
- preventing the processor from writing to the first segment while in the first state unless the processor requests ownership of the first segment.
Dependencies are inferred from the claim text.