Pseudo least-recently-used (PLRU) replacement method for a multi-node snoop filter
AssigneeIntel Corporation
InventorsLinda J. Rankin, Kai Cheng
Life of this patent
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Abstract
A Snoop Filter for use in a multi-node processor system including different nodes of multiple processors and corresponding processor caches is provided with a Pseudo Least-Recently-Used (PLRU) replacement algorithm to identify a least-recently-used (PLRU) line from the plurality of lines in the cache array for update to reflect lines that are replaced in the processor caches.
Claims22
A Snoop Filter for use in a multi-node processor system including different nodes of multiple processors and corresponding processor caches, comprising:
- a cache array to store data information in a plurality of lines;
- and
- a replacement mechanism responsive to a processor transaction to identify a least-recently-used (LRU) line from the plurality of lines in the cache array for update to reflect lines that are replaced in one or more processor caches.
A Pseudo Least-Recently-Used (PLRU) replacement method for a multi-node Snoop Filter including a plurality of lines storing data information, comprising:
- determining if a processor transaction is one of a processor memory read (RM), a processor read for ownership (RO), a clean line replacement (CLR), and a processor write (W);
- determining if a Snoop Filter cache array has a line associated with the processor transaction, if the processor transaction is one of the processor memory read (RM) and the processor read for ownership (RO);
- if the cache array has a line associated with the processor transaction indicating a HIT condition, selecting a corresponding entry (way) as a most-recently used (MRU);
- if the cache array does not have a line associated with the processor transaction indicating a MISS condition, selecting a victim entry (way) using a LRU vector and making the victim entry (way) as MRU;
- and
- selecting a corresponding way as LRU, if the processor transaction is one of the clean line replacement (CLR) and the processor write (W).
A multi-node processor system, comprising:
- one or more processor nodes each including a plurality of processors with processor caches;
- one or more I/O nodes each including an I/O bridge with a private I/O cache;
- and
- a Snoop Filter operatively connected to the processor nodes and the I/O nodes to manage data information related to cache lines in one or more processor caches, said Snoop Filter comprising a cache array to store data information in a plurality of lines, and a Pseudo Least-Recently-Used (PLRU) replacement mechanism responsive to a processor transaction to identify a least-recently-used (LRU) line from the plurality of lines in the cache array for update to reflect lines that are replaced in one or more processor caches.
Dependencies are inferred from the claim text.