Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter
AssigneeAltera Corporation
InventorsAndy L. Lee, Brian Johnson, Richard G. Cliff
Life of this patent
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Abstract
First-in/first-out (“FIFO”) memory circuitry includes first and second Gray-code-based counters for respectively counting write and read clock signals. A Gray code subtractor subtracts from one another the counts output by the counters. Shift register circuitry shifts in successive data words in synchronism with the write clock signal. The shift register circuitry includes selection circuitry configured to select one of the data words based on a Gray code decoding of information from the subtractor. Circuitry may also be included to monitor the information from the subtractor to detect full or empty conditions of the shift register circuitry.
Claims33
First-in/first-out memory circuitry comprising:
- first and second Gray code counter circuitries respectively counting write and read clock signals;
- Gray code subtractor circuitry subtracting counts provided by the counter circuitries;
- and
- shift register circuitry shifting in write data words in synchronism with the write clock signal and outputting one of those data words selected based on subtraction information from the subtractor circuitry, wherein:
- the first counter circuitry counts at twice the write clock rate and the second counter circuitry counts in double increments of the Gray code.
First-in/first-out memory circuitry comprising:
- write counter circuitry configured to count, in a Gray code, half cycles of a write clock signal that is synchronized with successive write data words;
- read counter circuitry configured to count, in double increments of the Gray code, a read clock signal;
- first shift register circuitry configured to shift in Gray code count data produced by the write counter and to output a Gray code count selected based on double-increment count data produced by the read counter circuitry;
- and
- second shift register circuitry configured to shift in write data words in synchronism with the write clock signal and to output a write data word selected based on the Gray code count output by the first shift register circuitry.
Gray code subtractor circuitry comprising:
- shift register circuitry receiving and shifting in a first data signal sequence based on a Gray code;
- and
- decoder circuitry receiving a second data signal sequence based on a double-increment Gray code and selecting for output a first data signal in the shift register circuitry based on the second data signal.
Dependencies are inferred from the claim text.