Bi-directional bus circuitry executing bi-directional data transmission while avoiding floating state
AssigneeRenesas Technology Corp.
InventorHiroshi Makino
Life of this patent
Estimating the term…
Abstract
A data bus included in a bi-directional bus circuitry is divided into a first bus node and a second bus node by a repeater circuit. The repeater circuit includes a first tristate buffer for amplifying and transmitting data from the first bus node to the second bus node, and a second tristate buffer connected in reverse direction. When the data bus is not used, the first and second tristate buffers are both activated, and the repeater circuit functions as a latch circuit. Therefore, in the bi-directional bus circuitry, even when the data bus is not used, the potential level of the data bus can be prevented from being left unfixed, ensuring stable operation.
Claims13
A bi-directional bus circuitry shared among a plurality of circuit blocks, comprising:
- a data bus divided into (J+1) (J:
- natural number being 1 or more than 1) bus nodes,
- each of said plurality of circuit blocks being connected to one of said (J+1) bus nodes;
- a potential fixing circuit provided corresponding to one of said (J+1) bus nodes, for setting potential level of corresponding said bus node to a prescribed potential when data is input to/output from none of said plurality of circuit blocks;
- J repeater circuits provided between adjacent said bus nodes respectively,
- each repeater circuit having
- a first signal transmitting circuit transmitting data from one to the other of said adjacent bus nodes, and
- a second signal transmitting circuit transmitting data from said the other to said one of said adjacent bus nodes;
- and
- an arbiter circuit receiving circuit block information for specifying a circuit block which is an object of data output, and controlling activation of said first and second signal transmitting circuits,
- said arbiter circuit activating, when said data is input to/output from none of said plurality of circuit blocks, either one of said first and second signal transmitting circuits in each repeater circuit, so that potential level of said bus node corresponding to said potential fixing circuit is transmitted to said data bus entirely.
A bi-directional bus circuitry shared among a plurality of circuit blocks, comprising:
- a data bus divided into (J+1) (J:
- natural number being 1 or more than 1) bus nodes,
- each of said plurality of circuit blocks being connected to one of said (J+1) bus nodes;
- J repeater circuits arranged between adjacent said bus nodes,
- each of said repeater circuits including
- a first signal transmitting circuit transmitting data from one to the other of said adjacent bus nodes, and
- a second signal transmitting circuit transmitting data from said the other to said one of said adjacent bus nodes;
- and
- an arbiter circuit receiving circuit information for specifying a circuit block which is an object of data output, and controlling activation of said first and second signal transmitting circuits in each of said repeater circuits,
- said arbiter circuit activating both of said first and second signal transmitting circuits in each of said repeater circuits when said data bus is not used, that is, when data is input to/output from none of said plurality of circuit blocks.
Dependencies are inferred from the claim text.