Monolithic GPS RF front end integrated circuit
AssigneeSiRF Technology, Inc.
InventorsRobert Tso, Richard Joseph McConnell
Life of this patent
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Abstract
A highly integrated GPS RF Front End which uses a single conversion stage employs an image rejection mixer stage to eliminate the need for an image reject RF bandpass filter. Also a relatively high sample rate A/D is employed which allows a timeless monolitic IF Filter to be used. The disclosure also discusses a GPS Front End topology that is easily integrated from industry standard building blocks. With the broad variation in potential receiver designs, the present invention includes some specific receiver topologies that lend themselves to a high level of integration. The specific designs presented here are comprised of industry standard building blocks and functions that have been described elsewhere in the related art.
Claims21
A highly integrated Global Positioning System (GPS) RF front end, comprising:
- a Radio Frequency Integrated Circuit (RFIC) including:
- a single stage downconverter using dual mixers;
- an I/Q Intermediate Frequency (IF) active filter, coupled to the downconverter;
- an Automatic Gain Control (AGC) amplifier, coupled to the downconverter;
- an Analog-to-Digital Converter (ADC), coupled to the AGC amplifier;
- and
- a frequency synthesizer section, wherein the noise bandwidth of the GPS RF front end is set by the IF active filter.
A highly integrated global positioning system (GPS) RF front end, comprising:
- a radio frequency integrated circuit comprising:
- a single stage downconverter comprising dual mixers;
- an I/Q intermediate frequency (IF) active filter coupled to the downconverter;
- an automatic gain control (AGC) amplifier coupled to the downconverter;
- an analog-to-digital converter coupled to the AGC amplifier;
- and
- a frequency synthesizer section comprising:
- a reference oscillator;
- a frequency doubler coupled to the reference oscillator;
- a divide-by-9 circuit coupled to the frequency doubler;
- a phase and frequency detector (PFD) coupled to the divide-by-9 circuit;
- a charge pump coupled to the PFD;
- a voltage controlled oscillator (VCO) coupled to the charge pump and to the downconverter;
- a divide-by-41 circuit coupled to the VCO;
- and
- a divide-by-7 circuit coupled between the divide-by-41 circuit and the PFD to make a phase locked loop;
- wherein the noise bandwidth of the GPS RF front end is set by the IF active filter.
A radio frequency integrated circuit (RFIC) for a global positioning system (GPS) front end, comprising:
- a single stage downconverter comprising dual mixers;
- an I/Q intermediate frequency (IF) active filter coupled to the downconverter for receiving an I-IF output and a Q-IF output therefrom;
- an I/Q combiner circuit coupled to the IF active filter for combining the filtered I-IF and Q-IF outputs received therefrom and outputting a single IF output signal;
- an automatic gain control (AGC) amplifier coupled to the I/Q combiner circuit for amplifying the single IF output signal;
- an analog-to-digital converter (ADC) coupled to the AGC amplifier;
- and
- a frequency synthesizer section, wherein the noise bandwith of the GPS RF front end is set by the IF active filter.
A radio frequency integrated circuit (RFIC) for a global positioning system (GPS) front end, comprising:
- a single stage downconverter comprising dual mixers;
- an oscillator communicating with the dual mixers for providing respective in-phase and quadrature-phase signals thereto;
- an I/Q intermediate frequency (IF) active filter coupled to the downconverter for receiving an I-IF output and a Q-IF output therefrom;
- an automatic gain control (AGC) amplifier coupled to the I/Q combiner circuit for amplifying the single IF output signal;
- an analog-to-digital converter (ADC) coupled to the AGC amplifier;
- and
- a frequency synthesizer section, wherein the noise bandwith of the GPS RF front end is set by the IF active filter.
Dependencies are inferred from the claim text.