US 6,856,659 B1Granted

Clock recovery method in digital signal sampling

AssigneeThomson Licensing

InventorJouet Pierrick

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Abstract

A clock recovery method in digital signal sampling wherein the clock is generated from a phase-locking loop or PLL which multiples a given frequency by a whole number. The method includes comparing the relative position of the signals with respect to the clock so as to determine whether a selected type of the clock transitions is in phase with the same type of signal transitions by: producing over a clock period several zones, one zone corresponding to the selected type of transitions; analysing the signal transitions relatively to the clock uplink or downlink transitions; cumulating in the corresponding zone the analysis results; determining on the basis of the accumulation whether the sampling clock frequency and/or phase needs to be modified or not. The invention is applicable to signals derived from graphics cards.

Claims8

Dependent claims

Device for synchronizing a sampling clock in the case of sampling digital signals comprising:

a phase lock loop (PLL) which multiplies a signal at a given frequency by an integer number, said PLL receiving a reference signal at an input thereof and outputting a clock signal,
means for formulating n analysis zones, said formulating means receiving the clock signal at an input and outputting signals determining the n analysis zones,
an analysis circuit for comparing, during a specified time, digital signals to signals determining the n analysis zones, counting by zone the results of the comparisons then testing the results of the comparisons in order to send either a phase correction signal to an input of a comparator, the other input receiving the reference signal and the output being connected to the PLL input or a frequency correction circuit sent to the input of the PLL to modify the integer number.

Dependencies are inferred from the claim text.