US 6,856,658 B1 · Digital PLL circuit operable in short burst interval

Abstract

A digital PLL (phase locked loop) circuit includes a sampling circuit, a plurality of internal circuits and an output switching circuit. The sampling circuit samples a burst data signal in response to a multi-phase clock signal to produce N (N is a positive integer larger than one) sampled data signals. The multi-phase clock signal includes N clock signals, each of which has substantially the same frequency as the data signal and which have phases different by a predetermined component from one after another. Each of the plurality of internal circuits is selected in response to a first selection signal, and outputs a set of a selected one of the N clock signals and an identified data signal from the N sampled data signals, which corresponds to the selected clock signal, in response to the selected clock signal, when the internal circuit is selected. The output switching circuit selects the set corresponding to the selected internal circuit from among the sets from the plurality of internal circuits based on a second selection signal.

Claims18

Dependent claims

A digital PLL (phase locked loop) circuit comprising:

a sampling circuit sampling a burst data signal in response to a multi-phase clock signal to produce N (N is a positive integer larger than one) sampled data signals, said multi-phase clock signal including N clock signals, each of which has substantially the same frequency as said data signal and which have phases different by a predetermined component from one after another;
a plurality of internal circuits, each of which is selected in response to a first selection signal, and outputting a set of a selected one of said N clock signals and an identified data signal from said N sampled data signals, which corresponds to said selected one of said N clock signals, in response to said selected one of said N clock signals, when said internal circuit is selected;
and
an output switching circuit selecting said set corresponding to said selected internal circuit from among said set from said plurality of internal circuits based on a second selection signal.

1 more element

A method of reducing a time interval between burst data signals in a digital PLL (phase locked loop) circuit, comprising:

(a) sampling a burst data signal in response to a multi-phase clock signal to produce N (N is a positive integer larger than one) sampled data signals, said multi-phase clock signal including N clock signals, each of which has substantially the same frequency as said data signal and which have phases different by a predetermined component from one after another;
(b) selecting one of a plurality of internal circuits other than a currently used internal circuit in response to a first selection signal;
(c) producing a set of a selected one of said N clock signals and an identified data signal from said N sampled data signals in response to said selected one of said N clock signals in said selected internal circuit;
and
(d) selecting one of said set from said plurality of internal circuits based on a second selection signal.

2 more elements

Dependencies are inferred from the claim text.

Digital PLL circuit operable in short burst interval

Life of this patent

Digital PLL circuit operable in short burst interval

Life of this patent

Abstract

Claims18