Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device

An integrated circuit comprising:

• a memory array having array lines on at least one layer exiting to a given side of the array;
• a decoder circuit for generating a plurality of decoder outputs;
• a plurality of array line driver circuits, each having an output coupled to a corresponding one of the array lines, a respective plurality of said array line driver circuits coupled to each respective decoder output, each array line driver circuit for coupling its corresponding array line to an associated one of a plurality of first bias nodes when its associated decoder output is selected, and for coupling its corresponding array line to an associated one of a plurality of second bias nodes when its associated decoder output is unselected;
• a plurality of first bias circuits for respectively generating a suitable condition on the plurality of first bias nodes;
• and
• a plurality of second bias circuits for respectively generating a suitable condition on the plurality of second bias nodes.

An integrated circuit comprising:

• a three-dimensional memory array having array lines of a first type on at least one layer;
• a plurality M of upper bias node circuits for respectively generating a suitable condition on a plurality M of upper bias nodes;
• a plurality N of lower bias node circuits for respectively generating on a plurality N of lower bias nodes a bias condition appropriate for unselected array lines on an associated layer;
• a decoder circuit comprising a plurality of decoder outputs;
• a plurality of array line driver circuits, each having an input coupled to an associated decoder output, and having an output coupled to a corresponding one of the array lines, wherein a respective plurality M of said array line driver circuits is associated with each respective decoder output, and wherein each respective array line driver circuit associated with a given decode node couples its corresponding array line at times to a respective one of the plurality M of upper bias nodes, and couples its corresponding array line at other times to an associated one of the plurality N of lower bias nodes.

An integrated circuit comprising:

• a three-dimensional memory array having array lines of a first type on each of at least two layers;
• a decoder circuit comprising a plurality of decoder outputs;
• a plurality of array line driver circuits, each baying an input coupled to an associated decoder output, and having an output coupled to a corresponding one of the array lines, wherein a respective plurality M of said array line driver circuits is associated with each respective decoder output;
• wherein each respective array line driver circuit associated with a given decode node couples its corresponding array line to a respective one of a plurality M of selected bias nodes when its associated decode node is selected, and couples its corresponding array line to an associated one of a plurality N of unselected bias nodes when its associated decode node is not selected;
• wherein the array line driver circuits associated with a given decode node correspond to at least two array lines on each of at least two layers of the memory array;
• a plurality M of selected bias circuits for respectively generating a suitable condition on the plurality M of selected bias nodes;
• and
• a plurality N of unselected bias circuits for respectively generating on the plurality N of unselected bias nodes a bias condition appropriate for unselected array lines on an associated one of the layers.

An integrated circuit comprising:

• a memory array having word lines and bit lines;
• a decoder circuit comprising a plurality of decoder outputs;
• and
• a respective word line driver circuit for each respective word line, each word line driver circuit responsive to an associated decoder output and having a first device for driving its associated word line to either a selected bias voltage or to an unselected bias condition conveyed on a first bus line, and having a second device for driving its associated word line to an unselected bias condition conveyed on a second bus line.