Apparatus for writing data bits to a memory array
AssigneeHewlett-Packard Development Company, L.P.
InventorMichael Christian Fischer
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Abstract
A method of writing data bits to a memory array. In one method embodiment, a first input is received. This causes an application of high power, via a sense line, to an addressed bit in the memory array and causes a write operation to be applied to the addressed bit. A second input is received. This causes an application of low power, via said sense line, to the addressed bit and causes a read operation on the addressed bit. The sense line is used to read and write the addressed bit.
Claims29
A circuit for writing a data bit to a memory array comprising:
- a power source for providing voltage potential and current to said circuit and coupled thereto;
- a input line for receiving inputted data bit values and coupled to a logic inverter;
- a plurality of first transistors having first leads coupled to said input line;
- a plurality of second transistors having first leads coupled to an output of said logic inverter;
- a plurality of sense lines coupled to other leads of said first and said second plurality of transistors and coupled to said memory array;
- a plurality of sense amplifiers coupled to other leads of said first and said second plurality of transistors;
- and
- a plurality of address lines coupled to said memory array and coupled to said sense lines, enabling writing of said data bit to an addressed bit of said memory array.
A circuit for writing a data bit to an addressed bit in a memory array comprising:
- a power source for providing voltage potential and current to said circuit and coupled thereto;
- a data bit input line for receiving inputted data bit values and coupled to a logic inverter;
- a first transistor having a first lead coupled to said data input line and a second lead coupled to a column sense line and a third lead coupled to a positive voltage, said positive voltage coupled to said circuit;
- a second transistor having a first lead coupled to an output of said logic inverter and a second lead coupled to an input of a column sense amplifier and a third lead coupled to said column sense line;
- a third transistor having a first lead coupled to said output of said logic inverter and a second lead coupled to a row sense line and a third lead coupled to an input of a row sense amplifier;
- and
- a fourth transistor having a first lead coupled to said input line and a second lead coupled to a negative voltage and a third lead coupled to said row address line, enabling writing of said data bit to said addressed bit.
A circuit for writing a data bit to a memory array comprising:
- a power source for providing voltage potential and current to said circuit and coupled thereto;
- a input line for receiving inputted data bit values and coupled to said memory array;
- a plurality of first transistors having first leads coupled to said input line;
- a plurality of second transistors having first leads coupled to said input line, and wherein said plurality of second transistors are complimentary to the polarity of said plurality of first transistors;
- a plurality of sense lines coupled to other leads of said first and said second plurality of transistors and coupled to said memory array;
- a plurality of sense amplifiers coupled to other leads of said first and said second plurality of transistors;
- and
- a plurality of address lines coupled to said memory array and coupled to said sense lines, enabling writing of said data bit to an addressed bit of said memory array.
Dependencies are inferred from the claim text.