Method and system for merging multiple fuse decompression serial bitstreams to support auxiliary fuseblow capability
AssigneeInternational Business Machines Corporation
InventorsErik A. Nelson, Michael R. Ouellette
Life of this patent
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Abstract
Multiple fuse decompression serial bitstreams support an auxiliary fuseblow capability utilizing on-chip storage and providing a composite capability of embedded memory address/data failure information. A multiple repair capability has an improved compression algorithm to compress fuse data with system level soft-set redundancy, and lends itself to self-repair design, and to provide repairs for temperature sensitive fails. An instruction based tester interface in a fuse control provides shift loaded instructions in which the sequence of test and fuse repair operations is variable to provide flexibility in the manufacturing, test and repair operations.
Claims26
In an integrated circuit having a memory, a system for repairing defects in the memory comprising:
- a set of primary fuses for correcting defects discovered in the memory during a first test;
- a set of secondary fuses for correcting defects discovered in the memory during a second test;
- circuitry for blowing the primary and secondary fuses in correspondence with discovered defects;
- and
- wherein a failing address register (FAR) in the memory is used as a shift register during compression and decompression of fuse repair data, and is used as a parallel loaded register during Built-In Self Test (BIST), and provides a serial fuse repair data stream to the memory.
In an integrated circuit having a memory, a method for repairing defects in the memory comprising:
- providing a set of primary fuses for correcting defects discovered in the memory during a first test;
- providing a set of secondary fuses for correcting defects discovered in the memory during a second test;
- blowing the primary and secondary fuses in correspondence with discovered defects;
- and
- using a failing address register (FAR) as a shift register in the memory during compression and decompression of fuse repair data, and using the FAR shift register as a parallel loaded register during Built-In Self Test (BIST), and to provide a serial fuse repair data stream to the memory.
In an integrated circuit having a plurality of separate RAM memories, a system for repairing defects in the plurality of separate RAM memories comprising:
- a fuse macro that is shared between the plurality of separate RAM memories, and comprising a set of primary fuses for correcting defects discovered during a first test performed on the plurality of separate RAM memories, resulting in first fuse repair data that is compressed and stored as compressed fuse repair data in the set of primary fuses, and a set of secondary fuses for correcting defects discovered during a second subsequent test performed on the plurality of separate RAM memories, resulting in second fuse repair data that is stored in the set of secondary fuses;
- circuitry for blowing the primary and secondary fuses in correspondence with discovered defects.
In an integrated circuit having a plurality of separate RAM memories, a method for repairing defects in the plurality of separate RAM memories comprising:
- providing a fuse macro that is shared between the plurality of separate RAM memories, and comprising a set of primary fuses for correcting defects discovered during a first test performed on the plurality of separate RAM memories, resulting in first fuse repair data that is compressed and stored as compressed fuse repair data in the set of primary fuses, and a set of secondary fuses for correcting defects discovered during a second subsequent test performed on the plurality of separate RAM memories, resulting in second fuse repair data that is stored in the set of secondary fuses;
- blowing the primary and secondary fuses in correspondence with discovered defects.
Dependencies are inferred from the claim text.